TDA9109A datasheet(31/47 Pages) STMICROELECTRONICS

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TDA9109A

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The TDA9109A also includes a Lock/Unlock iden-

tification block which senses in real time whether

PLL1 is locked or not on the incoming horizontal

sync signal.

The lock/unlock information is available through

the I2C read and the pin 3 voltage level

PLL1 Timing Diagram

Figure 10.

2.3 PLL2

PLL2 ensures a constant position of the shaped

flyback signal in comparison with the sawtooth of

the VCO, taking into account the saturation time

Ts (see Figure 11)

Figure 11. PLL2 Timing Diagram

The phase comparator of PLL2 (phase type com-

parator) is followed by a charge pump (typical out-

put current: 0.5 mA).

The flyback input consists of an NPN transistor.

This input must be current driven. The maximum

recommended

input

current

5 mA

(see Figure 12).

Figure 12. Flyback Input Electrical Diagram

The duty cycle is adjustable through I

2C from 30 %

to 65 %. For a safe start-up operation, the initial

duty cycle (after power-on reset) is 65% in order to

avoid having too long a conduction period of the

horizontal scanning transistor.

The maximum storage time (Ts Max.) is (0.44TH-

TFLY/2). Typically, TFLY/TH is around 20 % which

means that Ts max is around 34 % of TH.

The PLL1 ensures the exact coincidence between the

signal phase REF and HSYNC. A

±10% T

H phase

adjustment is possible around the 3.4V point.

Phase REF1 is obtained by comparison between

the sawtooth and a DC voltage adjustable between

2.9 V and 4.2 V.

HO SC

Sawtooth

7/8 TH

1/8 TH

6.4V

Ref. for H Position

(2.9V<Vb<4.2V)

1.6V

REF1

HSync

HOsc

Sawtooth

7/8TH

1/8 TH

Flyback

Internally

shaped Flyback

HDrive

Duty Cycle

1.6V

4.0V

6.4V

500

Ω

HFly

GND 0V

20k

Ω

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