TDA9109A datasheet(30/47 Pages) STMICROELECTRONICS

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TDA9109A

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The PLL1 is internally inhibited during extracted

vertical sync (if any) to avoid taking in account

missing pulses or wrong pulses on phase

comparator. Inhibition is obtained by stopping high

and low signals at the entry of the charge pump

block (see Figure 8).

Figure 8.

Figure 9.

The VCO uses an external RC network. It delivers

a linear sawtooth obtained by the charge and the

discharge of the capacitor, with a current propor-

tional to the current in the resistor. The typical

thresholds of the sawtooth are 1.6 V and 6.4 V.

The control voltage of the VCO is between 1.4 V

and 6.4 V (see Figure 9). The theoretical frequen-

cy range of this VCO is in the ratio of 1 to 4.5. The

effective frequency range has to be smaller (1 to

4.2) due to clamp intervention on the filter lowest

value.

The sync frequency must always be higher than

the free running frequency. For example, when us-

ing a sync range between 24.8 kHz and 100 kHz,

the suggested free running frequency is 23 kHz.

PLL1 ensures the coincidence between the lead-

ing edge of the sync signal and a phase reference

obtained by comparison between the sawtooth of

the VCO and an internal DC voltage which is I2C

adjustable between 2.9 V and 4.2 V (correspond-

ing to

±10 %) (see Figure 10).

TDA9109A Datasheet(PDF) 30 Page - STMicroelectronics