TMDS261 datasheet(35/42 Pages) TI

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TMDS261 Read Phase 1

TMDS261 Read Phase 2

TMDS261

www.ti.com............................................................................................................................................................................................ SLLS953 – DECEMBER 2008

generating a start condition followed by the TMDS261 I2C address (as shown following for a read operation), in

MSB first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the TMDS261, the I2C

master receives one byte of data from the TMDS261. The master can continue receiving data byes by issuing an

acknowledge after each byte read (steps 10, 11). After the last data byte has been transferred from the

TMDS261 to the master, the master generates a not-acknowledge followed by a stop.

Step 1

I2C start (master)

Step 2

I2C general address (master)

Step 3

I2C acknowledge (slave)

Step 4

I2C write sink logic address (master)

Addr

Where Addr is determined by the values shown in Table 7.

Step 5

I2C acknowledge (slave)

Step 6

I2C stop (master)

Step 6 is optional.

Step 7

I2C start (master)

Step 8

I2C general address (master)

Step 9

I2C acknowledge (slave)

Step 10

I2C read data (slave)

Data

Where data is determined by the logic values contained in the internal registers.

Step 11A

I2C acknowledge (master)

If Step 11A is executed, go to step 10. If Step 11B is executed, go to Step 12.

Step 11B

I2C not acknowledge (master)

Step 12

I2C stop (master)

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