DESCRIPTION (CONTINUED)

TMDS261

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

When any of the input ports are selected, the integrated terminations (50-

Ω termination resistors pulled up to

VCC) are switched on for the TMDS clock channel, the TMDS clock-detection circuit is enabled, and the DDC

repeater is enabled. After a valid TMDS clock is detected, the integrated termination resistors for the data lines

are enabled, and the output TMDS lines are enabled. When an input port is not selected, the integrated

terminations are switched off, the TMDS receivers are disabled, and the DDC repeater is disabled.

Clock-detection circuitry provides an automatic power-management feature, because if no valid TMDS clock is

detected, the terminations on the input TMDS data lines are disconnected and the TMDS outputs are placed in a

high-impedance state.

NOTES section.)

buffer output-voltage-select (OVS) settings (See the DDC I2C Function Description for detailed description on

TMDS input-port selection can be set. See Table 8 through Table 11.

GPIO mode: When the I2C_SEL pin is set high, the device is in GPIO control mode. The port selection is

controlled with source selectors, S1 and S2. The power-saving mode is controlled through the LP pin. In GPIO

mode, the default TMDS output edge rate that is the fastest setting of rise and fall time is set, and the default

Following are some of the key features (advantages) that TMDS261 provides to the overall sink-side system

(HDTV).

• 2×1 switch that supports TMDS data rates up to 3 Gbps on all two input ports.

• ESD: Built-in support for high ESD protection (up to 10 kV on the HDMI source side). The HDMI source-side

pins on the TMDS261 are connected via the HDMI/DVI exterior connectors and cable to the HDMI/DVI

sources (e.g., DVD player). In TV applications, it can be expected that the source side may be subjected to

higher ESD stresses compared to the sink side that is connected internally to the HDMI receiver.

• Adaptive equalization: The built-in adaptive equalization support compensates for intersymbol interference

[ISI] loss of up to 20 dB, which represents a typical 20-m HDMI/DVI cable at 3 Gbps. Adaptive equalization

adjusts the equalization gain automatically, based on the cable length and the incoming TMDS data rate.

• TMDS clock-detect circuitry: This feature provides an automatic power-management feature and also ensures

that the TMDS output port is turned on only if there is a valid TMDS input signal. TMDS clock-detect feature

circuitry during normal operation. However, for HDMI compliance testing (TMDS Termination Voltage Test),

the clock detect feature should be disabled by using the I2C Mode control. If the customer requires to pass

TMDS Termination Voltage Test in GPIO mode with default TMDS clock-detect circuitry enabled, then a valid

TMDS clock should be provided for this complaince test, so that the terminations on the TMDS data pair can

be connected and thus customer can pass the TMDS Termination Voltage Test.

helping the sink system to pass system-level compliance.

• Robust TMDS receive stage: This feature ensures that the TMDS261 can work with TMDS input signals

having common-mode voltage levels that can be either compliant or non-compliant with HDMI/DVI

specifications.

• VSadj: This feature adjusts the TMDS output swing and can help the sink system to tune the output TMDS

swing of the TMDS261 (if needed) based on the system requirements.

• TMDS output edge-rate control: This feature adjusts the TMDS261 TMDS output rise and fall times. There

are four settings of the rise and fall times that can be chosen. The default setting is the fastest rise and fall

2

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