PCM3168APAPR datasheet(32/66 Pages) TI

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MDI

(1)

'0'

ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

W ADR6

MDI

(1)

'1'

ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

Don'tCare(X)

W ADR6

MDO

Hi-Z

PCM3168A

PCM3168A-Q1

SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com

Figure 48 shows the functional timing diagram for single write operations on the serial control port. MS is held at

a high state until a register must be written. To start the register write cycle, MS is set to a low state. 16 clocks

are then provided on MC, corresponding to the 16 bits of the control data word on MDI. After the 16th clock cycle

has been completed, MS is set high to latch the data into the indexed mode control register.

Also, the PCM3168A and PCM3168A-Q1 support multiple write operations in addition to single write operations,

which can be performed by sending the following N-times of the 8-bit register data after the first 16-bit register

address and register data while keeping the MC clocks and MS at a low state. Closing a multiple write operation

can be accomplished by setting MS to a high state.

(1) X = Don't care.

Figure 48. Register Write Operation

Figure 49 shows the functional timing diagram for single read operations on the serial control port. MS is held at

a high state until a register must be read. To start the register read cycle, MS is set to a low state. 16 clocks are

then provided on MC, corresponding to the first eight bits of the control data word on MDI and the second eight

bits of the read-back data word from MDO. After the 16th clock cycle has been completed, MS is held high for

the next write or read operation. MDO remains in a high impedance state except during the eight MC clock

periods of the actual data transfer.

(1) X = Don't care.

Figure 49. Register Read Operation

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PCM3168APAPR Datasheet(PDF) 32 Page - Texas Instruments

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