PCM3168APAPR datasheet(34/66 Pages) TI

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PACKET PROTOCOL

SDA

SCL

SlaveAddress

R/W

(1)

ACK

(2)

DATA

(3)

ACK

DATA

ACK

1to7

1to8

ACK

Start

Condition

Stop

Condition

WRITE OPERATION

Transmitter

DataType

SlaveAddress

ACK

RegAddress

ACK

WriteData1

ACK

WriteData2

ACK

READ OPERATION

Transmitter

SlaveAddress

ACK

RegAddress

ACK

SlaveAddress

ACK

ReadData

NACK

DataType

PCM3168A

PCM3168A-Q1

SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com

A master device must control the packet protocol, which consists of the start condition, slave address with the

read/write bit, data if a write operation is required, acknowledgement if a read operation is required, and stop

condition. The PCM3168A and PCM3168A-Q1 support both slave receiver and transmitter functions. Details

about DATA for both write and read operations are described in Figure 52.

(1) R/W: Read operation if '1'; write operation otherwise.

(2) ACK: Acknowledgement of a byte if '0', not Acknowledgement of a byite if '1'.

(3) DATA: Eight bits (byte); details are described in the Write Operation and Read Operation sections.

Figure 52. DATA Operation

The PCM3168A and PCM3168A-Q1 support a receiver function. A master device can write to any PCM3168A

and PCM3168A-Q1 register using single or multiple accesses. The master sends a PCM3168A and

PCM3168A-Q1 slave address with a write bit, a register address, and the data. If multiple access is required, the

address is that of the starting register, followed by the data to be transferred. When the data are received

properly, the index register is incremented by one automatically. When the index register reaches &h5E, the next

value is &h40. When undefined registers are accessed, the PCM3168A and PCM3168A-Q1 do not send an

acknowledgement. Figure 53 illustrates a diagram of the write operation. The register address and write data are

in 8-bit, MSB-first format.

(1) M = Master device, S = Slave device, St = Start condition, W = Write, ACK = Acknowledge, and Sp = Stop condition.

Figure 53. Framework for Write Operation

A master device can read the registers from &h40 to &h5E of the PCM3168A and PCM3168A-Q1. The value of

the register address is stored in an indirect index register in advance. The master sends the PCM3168A and

PCM3168A-Q1 slave address with a read bit after storing the register address. Then the PCM3168A and

PCM3168A-Q1 transfer the data that the index register points to. Figure 54 shows a diagram of the read

operation.

(1) M = Master device, S = Slave device, St = Start condition, Sr = Repeated start condition, W = Write, R = Read, ACK = Acknowledge,

NACK = Not acknowledge, and Sp = Stop condition.

NOTE: The slave address after the repeated start condition must be the same as the previous address.

Figure 54. Framework for Read Operation

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Product Folder Link(s): PCM3168A PCM3168A-Q1

PCM3168APAPR Datasheet(PDF) 34 Page - Texas Instruments

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