PCM3168APAPR datasheet(60/66 Pages) TI

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MODE Pin

RST Pin

OVF Pin

System Clock and Audio Interface Clocks

PowerPAD

External Mute Control

PCM3168A

PCM3168A-Q1

SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com

This pin is a logic input with quad-state input capability. The MODE pin is high when connected to VDD, low

when connected to DGND, and pulled up or pulled down through an external resistor and for the two mid-states

in order to distinguish the four input states. The pull-up or pull-down resistor must be 220 k

Ω, ±5% in tolerance.

Note that the state of the MODE pin is only sampled by a power-on or a low-to-high transition of the RST pin.

When the MODE pin setting changes to change the operating mode, the new mode setting does not take effect

immediately; a RST pin toggle is required to make the new mode setting valid, and for the new mode to take

effect.

The OVF pin has two functions. It is primarily the flag for ADC overflow occurrence detection. It is also used to

indicate that the internal reset sequence is complete and that the device is ready to enter serial mode control.

The quality of SCKI may influence dynamic performance, because the PCM3168A and PCM3168A-Q1 (both the

ADC and DAC) operate based on SCKI. Therefore, it may be required to consider the jitter, duty, and rise/fall

time of the system clock.

In slave mode, the PCM3168A and PCM3168A-Q1 do not require a specific timing relationship between

BCKAD/LRCKAD and SCKI, and BCKDA/LRCKDA and SCKI; however, there is a possibility of performance

degradation with a certain timing relationship between them. In that case, specific timing relationship control

might resolve this performance degradation.

In master mode, there is a possibility of performance degradation because of heavy loads on BCKAD/LRCKAD,

BCKDA/LRCKDA, and DOUT1/2/3. It is recommended to load these pins as lightly as possible. Note that all

output clocks and signals go low; they do not go into a high-impedance state during power-save mode.

The PowerPAD of the PCM3168A and PCM3168A-Q1 is internally connected to the substrate of the silicon. It

should be connected to the ground plane with sufficient low conductance in electrical and thermal; see Figure 56.

The PowerPAD size is 7,25 mm x 7,00 mm (0,725 cm × 0.7 cm).

For power-down ON/OFF control without the pop-noise that is generated by a dc level change on the DAC

output, the external mute control is generally required. Use of the following control sequence is recommended:

external mute ON, codec power-down ON, SCKI stop and resume if necessary, codec power-down OFF, and

external mute OFF control.

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Product Folder Link(s): PCM3168A PCM3168A-Q1

PCM3168APAPR Datasheet(PDF) 60 Page - Texas Instruments

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