PCM3168APAPR datasheet(20/66 Pages) TI

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VOLTAGE REFERENCES

SYSTEM CLOCK INPUT

SystemClock

(SCKI)

High

Low

SCL

SCH

SCY

2.0V

0.8V

SAMPLING MODE

PCM3168A

PCM3168A-Q1

SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com

The PCM3168A and PCM3168A-Q1 include two internal references for the six-channel ADCs; these references

correspond to the outputs VREFAD1 and VREFAD2. Both reference pins should be connected with an analog

ground via decoupling capacitors. In addition, the PCM3168A and PCM3168A-Q1 include two pins for

common-mode voltage output (VCOMDA for DACs and VCOMAD for ADCs). These pins should be also

connected with an analog ground via decoupling capacitors. Furthermore, both common pins can be used to bias

external high-impedance circuits, if they are required.

The PCM3168A and PCM3168A-Q1 require an external system clock input applied at the SCKI input for ADC

and DAC operation. The system clock operates at an integer multiple of the sampling frequency, or fS. The

multiples supported in ADC operation include 256 fS, 384 fS, 512 fS, and 768 fS; the multiples supported in DAC

operation include 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, and 768 fS. Details for these system clock multiples are

shown in Table 3. Figure 30 and Table 4 show the SCKI timing requirements.

Table 3. System Clock Frequencies for Common Audio Sampling Rates

SAMPLING

DEFAULT

FREQUENCY

SYSTEM CLOCK FREQUENCY (MHz)

SAMPLING

MODE

fS (kHz)

128 fS

(1)

192 fS

(1)

256 fS

384 fS

512 fS

768 fS

N/A

2.0480

3.0720(2)

4.0960

6.1440

2.0480(1)

3.0720(1)

4.0960

6.1440(2)

8.1920

12.2880

Single rate

4.0960(1)

6.1440(1)

8.1920

12.2880(2)

16.3840

24.5760

44.1

5.6488(1)

8.4672(1)

11.2896

16.9344(2)

22.5792

33.8688

6.1440(1)

9.2160(1)

12.2880

18.4320(2)

24.5760

36.8640

88.2

11.2896(3)

16.9344(3)

22.5792

33.8688

N/A

Dual rate

12.2880(3)

18.4320(3)

24.5760

36.8640

N/A

176.4(3)

22.5792(3)

33.8688(3)

N/A

Quad rate(3)

192(3)

24.5760(3)

36.8640(3)

N/A

(1)

Supported only by DAC operation

(2)

Requires 50% duty cycle for stable ADC performance.

(3)

Supported only by DAC operation

Figure 30. System Clock Timing Requirements

Table 4. Timing Requirements for Figure 30

SYMBOL

PARAMETER

MIN

MAX

UNIT

tSCY

System clock pulse cycle time

tSCH

System clock pulse width high

tSCL

System clock pulse width low

tDTY

System clock pulse duty cycle

The PCM3168A and PCM3168A-Q1 support two sampling modes (single rate and dual rate) in ADC operation,

and three sampling modes (single rate, dual rate, and quad rate) in DAC operation. In single rate mode, the ADC

and DAC operate at an oversampling frequency of x128 (except when SCKI = 128 fS and 192 fS). This mode is

supported for sampling frequencies less than 50 kHz. In dual rate mode, the ADC and DAC operate at an

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