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ATA5423-PLSW Datasheet(PDF) 91 Page - ATMEL Corporation |
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ATA5423-PLSW Datasheet(HTML) 91 Page - ATMEL Corporation |
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91 / 100 page  91 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 16. Digital Timing Characteristics All parameters refer to GND and are valid for T amb =25°C. VVS1 =VS2 = 3.0V (1 Li battery application (3V)), VVS2 = 6.0V (2 Li battery application (6V)) and VVS2 =5.0V (Base-station Application(5V)) unless otherwise specified. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 12 Basic Clock Cycle of the Digital Circuitry 12.1 Basic clock cycle TDCLK 16/fXTO 16/fXTO µs A 12.2 Extended basic clock cycle XLIM = 0 BR_Range_0 BR_Range_1 BR_Range_2 BR_Range_3 XLIM = 1 BR_Range_0 BR_Range_1 BR_Range_2 BR_Range_3 T XDCLK 8 4 2 1 × T DCLK 16 8 4 2 × T DCLK 8 4 2 1 × T DCLK 16 8 4 2 × T DCLK µs A 13 RX Mode/RX Polling Mode 13.1 Sleep time Sleep and XSleep are defined in control register 4 T Sleep Sleep × X Sleep × 1024 × T DCLK Sleep × X Sleep × 1024 × T DCLK ms A 13.2 Start -up PLL RX mode from IDLE mode TStartup_PLL 798.5 × TDCLK 798.5 × TDCLK µs A 13.3 Start -up signal processing BR_Range_0 BR_Range_1 BR_Range_2 BR_Range_3 T Startup_Sig_Proc 882 498 306 210 × T DCLK 882 498 306 210 × T DCLK A 13.4 Time for bit check Average time during polling. No RF signal applied. fSignal = 1/(2 × tee) Signal data rate Manchester (Lim_min and Lim_max up to ±50% of t ee, see Figure 9-4 on page 56) Bit -check time for a valid input signal fSignal NBit-check = 0 N Bit-check = 3 NBit-check = 6 NBit-check = 9 TBit_check 3/f Signal 6/fSignal 9/fSignal 1/fSignal 3.5/f Signal 6.5/fSignal 9.5/fSignal ms C 13.5 Bit -rate range BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range 1.0 2.0 4.0 8.0 2.5 5.0 10.0 20.0 Kbit/s A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter |
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