ATA5423-PLSW datasheet(57/100 Pages) ATMEL

57 / 100 page

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

For the best noise immunity, use of a low span between T

Lim_min and TLim_max is recommended.

This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst: a

“11111...” or a “10101...” sequence in Manchester or Bi-phase is a good choice. A good compro-

mise between sensitivity and susceptibility to noise regarding the expected edge-to-edge time,

ee, is a time window of ±38%; to get the maximum sensitivity the time window should be ±50%

and then N

Bit-check ≥ 6. Using preburst patterns that contain various edge-to-edge time periods,

the bit-check limits must be programmed according to the required span.

The bit-check limits are determined by means of the formula below:

Lim_min = Lim_min × TXDCLK

Lim_max = (Lim_max -1) × TXDCLK

Lim_min is defined by the bits Lim_min 0 to Lim_min 5 in control register 5.

Lim_max is defined by the bits Lim_max 0 to Lim_max 5 in control register 6.

Using the above formulas, Lim_min and Lim_max can be determined according to the required

Lim_min, TLim_max and TXDCLK. The time resolution defining TLim_min and TLim_max is TXDCLK. The

minimum edge-to-edge time t

ee is defined in the section “Receiving Mode” on page 59. The

lower limit should be set to Lim_min

≥ 10. The maximum value of the upper limit is

Lim_max = 63.

Figure 9-5, Figure 9-6, and Figure 9-7 illustrate the bit check for the bit-check limits

Lim_min = 14 and Lim_max = 24. The signal processing circuits are enabled during T

Startup_PLL

and T

Startup_Sig_Proc. The output of the ASK/FSK demodulator (Demod_Out) is undefined during

that period. When the bit check becomes active, the bit-check counter is clocked with the cycle

XDCLK.

Figure 9-5 shows how the bit check proceeds if the bit-check counter value CV_Lim is within the

limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In Figure 9-6 on

page 58 the bit check fails because the value CV_Lim is lower than the limit Lim_min. The bit

check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 9-7 on page 58.

Figure 9-5.

Timing Diagram During Bit Check

Bit check ok

Bit check mode

Start-up mode

1/2 Bit

RX_ACTIVE

(Lim_min = 14, Lim_max = 24)

Demod_Out

Bit-check counter

Bit check

Startup_Sig_Proc

Bit-check

XDCLK

1 2 345 67 81 2 3 45 6789 10 1112131415161718 1 23 4 5 6 7 8 9 10 11

1213 1415 1 2 3 4 5 67

ATA5423-PLSW Datasheet(PDF) 57 Page - ATMEL Corporation

ATA5423-PLSW Datasheet(HTML) 57 Page - ATMEL Corporation

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