ATA5423-PLSW datasheet(47/100 Pages) ATMEL

47 / 100 page

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

7.7

Low Battery Indicator

The status bit Low_Batt is set to “1” if the voltage V

VSOUT on pin VSOUT drops below 2.38V

(typically).

Low_Batt is set to “0” if V

VSOUT exceeds VThres_2 and the status register is read via the 4-wire

serial interface (see Figure 5-3 on page 34).

Figure 7-5.

Timing Status Bit Low_Batt

7.8

Pin VAUX

To switch the transceiver from OFF to AUX mode, the voltage V

VAUX on pin VAUX must exceed

3.5V (typically) (see Figure 7-6 on page 48). If V

VAUX exceeds 2V (typically) pin N_RESET is set

to low, and DVCC and the power supply for external devices VSOUT are switched on.

If V

VAUX exceeds 3.5V (typically) the status bit P_On_Aux is set to “1” and an interrupt is issued.

After the voltage on pin VSOUT exceeds 2.3V (typically) and the start-up time of the XTO is

elapsed, the output clock on pin CLK is available. Because the enabling of pin CLK is asynchro-

nous, the first clock cycle may be incomplete. N_RESET is set to high if V

VSOUT exceeds 2.38V

(typically) and the XTO is settled.

If the transceiver is in any active mode (IDLE, TX, RX, RX_Polling), a positive edge on pin VAUX

and V

VAUX > VS1 + 0.5V sets P_On_Aux to “1”. The state transition P_On_Aux 0 →1 generates

an interrupt. If P_On_Aux is still “1” during the positive edge on pin VAUX no interrupt is issued.

P_On_Aux and the interrupt are deleted after reading the status register.

IDLE, AUX, TX, RX

RX Polling Mode

Read Status Register

VVSOUT < 2.38V (typ)

Low_Batt = 1

ATA5423-PLSW Datasheet(PDF) 47 Page - ATMEL Corporation