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ATA5423-PLSW Datasheet(PDF) 27 Page - ATMEL Corporation |
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ATA5423-PLSW Datasheet(HTML) 27 Page - ATMEL Corporation |
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27 / 100 page  27 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 Figure 4-2. XTO Block Diagram To find the right values used in control registers 2 and 3 (see Table 7-7 and Table 7-10), the relationship between f XTO and the fRF is shown in Table 4-1 on page 28. To determine the right content, the frequency at pin CLK as well as the output frequency at RF_OUT in ASK mode can be measured, then the FREQ value can be calculated according to Table 4-1 on page 28 so that f RF is exactly the desired radio frequency. 8 pF 8 pF XTAL1 Divider /16 CLK_ON (control register 3) VSOUT_OK (from power supply) DVCC_OK (from power supply) Baud1 In IDLE mode and during Sleep mode (RX_Polling) the switches S1 and S2 are open. XLim Baud0 & Divider /3 XTO_OK (to reset logic) Divider /1 /2 /4 /8 /16 10 pF 10 pF Amplitude detector S2 S1 fXDCLK XTAL2 CLK CL2 CL1 fXTO fDCLK |
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