ATA5423-PLSW datasheet(40/100 Pages) ATMEL

40 / 100 page

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

7.3.3

Control Register 3 (ADR 2)

7.3.4

Control Register 4 (ADR 3)

Table 7-10.

Control Register 3

(Function of Bit 7, Bit 6, Bit 5, Bit 4, Bit 3 and Bit 2)

FR12

212

FR11

211

FR10

210

FR9

FR8

FR7

Function

000

FREQ3 = 0

000

FREQ3 = 128

001

FREQ3 = 256

...

FREQ3 = 3840 (default)

...

111

FREQ3 = 7936

111

FREQ3 = 8064

Note:

Tuning of f

RF MSBs

Table 7-11.

Control Register 3 (Function of Bit 1)

VSOUT_EN

Function

Output voltage power supply for external devices off (pin VSOUT)

Output voltage power supply for external devices on (default)

Note:

This bit is set to “1” if the bit check is OK (RX_Polling, RX mode), an event at pin T1, T2, T3, T4 or

T5 occurs or the bit Power_On in the status register is “1”.

Setting VSOUT_EN = 0 in AUX mode is not allowed

Table 7-12.

Control Register 3 (Function of Bit 0)

CLK_ON

Function

Clock output off (pin CLK)

Clock output on (default)

Note:

This bit is set to “1” if the bit check is OK (RX_Polling, RX mode), an event at pin T1, T2, T3, T4 or

T5 occurs or the bit Power_On in the status register is “1”.

Table 7-13.

Control Register 4 (Function of Bit 7)

ASK_NFSK

Function (TX Mode, RX Mode)

FSK mode (default)

ASK mode

ATA5423-PLSW Datasheet(PDF) 40 Page - ATMEL Corporation

ATA5423-PLSW Datasheet(HTML) 40 Page - ATMEL Corporation

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