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AT88SC0104C Datasheet(PDF) 27 Page - ATMEL Corporation |
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AT88SC0104C Datasheet(HTML) 27 Page - ATMEL Corporation |
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27 / 58 page  24 5210B–SMIC–11/08 AT88SC0104/0204/0404/0808/1616/3216/6416/12816/25616C 7. Synchronous Protocol Communication with the CryptoMemory using the synchronous protocol is very similar to com- munication with AT24Cxxx Serial EEPROM devices using a two-wire protocol (TWI). Basic command structure and timing are the same however a significant difference exists when read- ing the CryptoMemory device that will be described below. 7.1 Start-up Sequence When first powering up the device, 5 pulses are required on CLK-SCL for reading of internal reg- isters. This may be accomplished by sending one full command byte to the device. The device will not respond but will then be ready to respond to the next correct command sequence. • Power-up V CC • External pull-up resistor pulls I/O-SDA high with V CC • After stable V CC, 5 pulses are applied to CLK-SCL • CLK-SCL and I/O-SDA may be driven. 7.2 Command Set The command set of CryptoMemory is expanded compared to a Serial EEPROM as the func- tionality of CryptoMemory exceeds that of a simple memory device. Each instruction sent to the CryptoMemory must have 4 bytes: Command, Address 1, Address 2 and N. The last byte, N, defines the number of any additional data bytes to be sent or received from the CryptoMemory device. Vcc I/O-SDA CLK-SCL 1 2 3 45 |
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