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AT88SC0104C Datasheet(PDF) 55 Page - ATMEL Corporation |
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AT88SC0104C Datasheet(HTML) 55 Page - ATMEL Corporation |
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55 / 58 page ![]() 52 5210B–SMIC–11/08 AT88SC0104/0204/0404/0808/1616/3216/6416/12816/25616C 10.2 Timing Diagrams for Synchronous Communications Figure 10-1. Bus Timing: SCL: Serial Clock, SDA: Serial Data I/O Figure 10-2. Write Cycle Timing: SCL: Serial Clock, SDA: Serial Data I/O Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. t WR (1) STOP CONDITION START CONDITION WORDn ACK 8th BIT SCL SDA |
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