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STM32W108HB Datasheet(PDF) 76 Page - STMicroelectronics |
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STM32W108HB Datasheet(HTML) 76 Page - STMicroelectronics |
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76 / 179 page  Serial interfaces STM32W108CB, STM32W108HB 76/179 Doc ID 16252 Rev 2 7.7.6 Transmit DMA end address register B (SCx_TXENDB) Address offset: 0xC814 (SC1_TXENDB) and 0xC014 (SC2_TXENDB) Reset value: 0x2000 0000 7.7.7 Transmit DMA count register (SCx_TXCNT) Address offset: 0xC828 (SC1_TXCNT) and 0xC028 (SC2_TXCNT) Reset value: 0x0000 0000 7.7.8 Receive DMA begin address register A (SCx_RXBEGA) Address offset: 0xC800 (SC1_RXBEGA) and 0xC000 (SC2_RXBEGA) Reset value: 0x2000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SC_TXENDB rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw [12:0] SC_TXENDB: Address of the last byte that will be read from the DMA transmit buffer B. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SC_TXCNT rw rw rw r r r r r rr rr rr r r [12:0] SC_TXCNT: The offset from the start of the active DMA transmit buffer from which the next byte will be read. This register is set to zero when the buffer is loaded and when the DMA is reset. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SC_RXBEGA rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw [12:0] SC_RXBEGA: DMA receive buffer A start address. |
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