STM32W108HB datasheet(45/179 Pages) STMICROELECTRONICS

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STM32W108CB, STM32W108HB

System modules

Doc ID 16252 Rev 2

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In the deep sleep state the STM32W108 waits for a wake up event which will return it to the

running state. In powering up the core logic the ARM® Cortex-M3 is put through a reset

cycle and ST software restores the stack and application state to the point where deep sleep

was invoked.

5.5.3

Further options for deep sleep

By default, the low-frequency internal RC oscillator (OSCRC) is running during deep sleep

(known as deep sleep 1).

To conserve power, OSCRC can be turned off during deep sleep. This mode is known as

deep sleep 2. Since the OSCRC is disabled, the sleep timer and watchdog timer do not

function and cannot wake the chip unless the low-frequency 32.768 kHz crystal oscillator is

used. Non-timer based wake sources continue to function. Once a wake event occurs, the

OSCRC restarts and becomes enabled.

5.5.4

Use of debugger with sleep modes

The debugger communicates with the STM32W108 using the SWJ.

When the debugger is connected, the CDBGPWRUPREQ bit in the debug port in the SWJ

is set, the STM32W108 will only enter deep sleep 0 (the Emulated Deep Sleep state). The

CDBGPWRUPREQ bit indicates that a debug tool is connected to the chip and therefore

there may be debug state in the system debug components. To maintain the state in the

system debug components only deep sleep 0 may be used, since deep sleep 0 will not

cause a power cycle or reset of the core domain. The CSYSPWRUPREQ bit in the debug

port in the SWJ indicates that a debugger wants to access memory actively in the

STM32W108. Therefore, whenever the CSYSPWRUPREQ bit is set while the STM32W108

is awake, the STM32W108 cannot enter deep sleep until this bit is cleared. This ensures the

STM32W108 does not disrupt debug communication into memory.

Clearing both CSYSPWRUPREQ and CDBGPWRUPREQ allows the STM32W108 to

achieve a true deep sleep state (deep sleep 1 or 2). Both of these signals also operate as

wake sources, so that when a debugger connects to the STM32W108 and begins accessing

the chip, the STM32W108 automatically comes out of deep sleep. When the debugger

initiates access while the STM32W108 is in deep sleep, the SWJ intelligently holds off the

debugger for a brief period of time until the STM32W108 is properly powered and ready.

For more information regarding the SWJ and the interaction of debuggers with deep sleep,

contact ST support for Application Notes and ARM® CoreSight documentation.

5.6

Security accelerator

The STM32W108 contains a hardware AES encryption engine accessible from the ARM®

Cortex-M3. NIST-based CCM, CCM*, CBC-MAC, and CTR modes are implemented in

hardware. These modes are described in the IEEE 802.15.4-2003 specification, with the

exception of CCM*, which is described in the ZigBee Security Services Specification 1.0.

STM32W108HB Datasheet(PDF) 45 Page - STMicroelectronics

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