TLE7809G datasheet(19/52 Pages) INFINEON

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Data Sheet

Rev. 3.01, 2008-04-15

TLE7809G

SPI (Serial Peripheral Interface)

Control and status information between SBC and

μC is exchanged via a digital interface, that is called “serial

peripheral interface” (SPI) on the SBC side, and “synchronous serial channel” (SSC) on the

μC side. The 16-bit

wide Programming or Input Word of the SBC (see Table 2 to Table 8) is read in via the data input DI (with “LSB

first”), which is synchronized with the clock input CLK supplied by the

μC. The Diagnosis or Output Word appears

synchronously at the data output DO (see Table 9).

The transmission cycle begins when the chip is selected by the Chip Select Not input CSN (“low” active). After the

CSN input returns from L to H, the word that has been read in becomes the new control word. The DO output

switches to tri-state status at this point, thereby releasing the DO bus for other usage.

The state of DI is shifted into the input register with every falling edge on CLK. The state of DO is shifted out of

the output register after every rising edge on CLK. The number of received input clocks is supervised by a modulo-

16 operation and the Input/Control Word is discarded in case of a mismatch.

This error is flagged by a “high” at the data output pin DO (interconnect to

μC: P1.4) of the following SPI output

word before the first rising edge of the clock is received. Additionally the logic level of DO will be “OR-ed” with the

logic level of DI (P1.3).

Note: After wake-up from low-power modes the device needs to be set to Active Mode first before switches like

LS1, LS2, Supply Output and LED Driver can be turned on with the second SPI command.

Figure 10

16-Bit SPI Input Data / Control Word

15 14 13 12 11 10

Mode Selection

Bits

Configuration

Select

Configuration Registers

Supply

Output

On/Off

Input

Data

Active

LIN Sleep

Sleep

Reserved

000

001

010

011

100

101

Reset

Thres*

Reset

Delay*

Window Watchdog Timing

Bit Position: 10 .. 5

MON2

On/Off*

MON3

On/Off*

MON4

On/Off*

110

111

LIN

10.4k*

MON1

On/Off*

ADC

Vbat/

Vtemp*

Reserved

(Watchdog Trigger Register )

LS1

On/Off

LS2

On/Off

MON5

On/Off*

not valid

Meas.

I/F

On/Off

Cyclic Wake Timing*

Bit Position: 9 .. 5

HS-LED

OV/UV

disable

HS-LED

On /Off

0**

not valid

LIN RxD Only

Stop

LSB

MSB

MS0

MS1

MS2

CS0

CS1

Reserved

* remains unchanged after Vcc-UV or WD-RESET

** if bit set to „1" command will be ignored

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