HT45R37 datasheet(67/100 Pages) HOLTEK

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HT45R37

Rev. 1.10

January 29, 2010

Fast Wake-Up

To minimise power consumption the device can enter

the SLEEP or IDLE Mode, where the clock source to the

device will be stopped. However when the device is

woken up again, it can take a considerable time for the

original system oscillator to restart, stabilise and allow

normal operation to resume. To ensure the device is up

and running as fast as possible a Fast Wake-Up function

is provided, which allows fSUB, namely either the RTC or

LIRC oscillator, to act as a temporary clock to first drive

the system until the original system oscillator has stabi-

lised. As the clock source for the Fast Wake-Up function

is the Watchdog Timer clock, the Watchdog Timer must

be enabled for this function to operate. If the Watchdog

Timer is not enabled then the Fast Start-up function can-

not be used. The Fast Wake-Up enable/disable function

is controlled using the configuration option.

If the Crystal oscillator is selected as the NORMAL

Mode system clock, and if the Fast Wake-Up function is

enabled, then it will take one to two tSUB clock cycles of

the LIRC or RTC oscillator for the system to wake-up.

The system will then initially run under the fSUB clock

source until 1024 Crystal clock cycles have elapsed, at

which point the HTO flag will switch high and the system

will switch over to operating from the Crystal oscillator.

If the ERC or HIRC oscillators or LIRC oscillator is used

as the system oscillator then it will take 1~2 clock cycles

of the ERC, HIRC or LIRC to wake up the system from

the SLEEP or IDLE Mode.

Note that if the Watchdog Timer is disabled, which

means that the RTC and LIRC are all both off, then there

will be no Fast Wake-Up function available when the de-

vice wakes-up from the SLEEP Mode.

Low Voltage Detector

- LVD

The Low Voltage Detect internal function provides a

means for the user to monitor when the power supply

voltage falls below a certain fixed level as specified in

the DC characteristics.

LVD Operation

The LVD function must be first enabled via a

configuration option after which bits 3 and 5 of the RTCC

LVD. Bit 3 is the enable/disable control bit and is known

as LVDC, when set low the overall function of the LVD

will be disabled. Bit 5 is the LVD detector output bit and

is known as LVDO. Under normal operation, and when

the power supply voltage is above the specified VLVD

value in the DC characteristic section, the LVDO bit will

remain at a zero value. If the power supply voltage

should fall below this VLVD value then the LVDO bit will

change to a high value indicating a low voltage condi-

tion. Note that the LVDO bit is a read-only bit. By polling

the LVDO bit in the RTCC register, the application pro-

gram can therefore determine the presence of a low

voltage condition.

After power-on, or after a reset, the LVD will be switched

off by clearing the LVDC bit in the RTCC register to zero.

Note that if the LVD is enabled there will be some power

consumption associated with its internal circuitry, how-

ever, by clearing the LVDC bit to zero the power can be

minimised. It is important not to confuse the LVD with

the LVR function. In the LVR function an automatic reset

will be generated by the microcontroller, whereas in the

LVD function only the LVDO bit will be affected with no

influence on other microcontroller functions.

There are a range of voltage values, selected using a

configuration option, which can be chosen to activate

the LVD.

Watchdog Timer

The Watchdog Timer is provided to prevent program

malfunctions or sequences from jumping to unknown lo-

cations, due to certain uncontrollable external events

such as electrical noise. It operates by providing a de-

vice reset when the Watchdog Timer counter overflows.

Watchdog Timer Operation

The Watchdog Timer clock source is provided by the in-

ternal clock, fS, which is in turn supplied by one of two

sources selected by configuration option: fSUB or fSYS/4.

Note that if the Watchdog Timer configuration option

has been disabled, then any instruction relating to its op-

eration will result in no operation.

Most of the Watchdog Timer options, such as en-

able/disable, Watchdog Timer clock source and clear in-

struction type are selected using configuration options.

In addition to a configuration option to enable the Watch-

dog Timer, there are four bits, WDTEN3~ WDTEN0, in

the MISC register to offer an additional enable control of

the Watchdog Timer. These bits must be set to a specific

value of 1010 to disable the Watchdog Timer. Any other

values for these bits will keep the Watchdog Timer en-

abled. After power on these bits will have the disabled

value of 1010.

One of the WDT clock sources is the internal fSUB, which

can be sourced from either the 32K_INT internal oscilla-

tor or the 32768Hz oscillator. The 32K_INT internal os-

cillator has an approximate period of 31.2

ms at a supply

voltage of 5V. However, it should be noted that this

specified internal clock period can vary with VDD, tem-

perature and process variations. The 32768Hz oscillator

is supplied by an external 32768Hz crystal. The other

Watchdog Timer clock source option is the fSYS/4 clock.

Whether the Watchdog Timer clock source is its own in-

ternal 32K_INT, the 32768Hz oscillator or fSYS/4, it is di-

vided by 2

13~216, using configuration option to obtain the

required Watchdog Timer time-out period. The max time

out period is when the 2

16 option is selected. This

HT45R37 Datasheet(PDF) 67 Page - Holtek Semiconductor Inc

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