HT45R37 datasheet(44/100 Pages) HOLTEK

44 / 100 page

HT45R37

Rev. 1.10

January 29, 2010

SPI Control Register

- SIMCTL2

The SIMCTL2 register is also used by the I

2C interface

but has the name SIMAR.

· TRF

The TRFbit is the Transmit/Receive Complete flag and

is set high automatically when an SPI data transmis-

sion is completed, but must be cleared by the applica-

tion program. It can be used to generate an interrupt.

· WCOL

The WCOL bit is used to detect if a data collision has

occurred. If this bit is high it means that data has been

attempted to be written to the SIMDR register during a

data transfer operation. This writing operation will be

ignored if data is being transferred. The bit can be

cleared by the application program. Note that using

the WCOL bit can be disabled or enabled via configu-

ration option.

· CSEN

The CSEN bit is used as an on/off control for the SCS

pin. If this bit is low then the SCS pin will be disabled

and placed into a floating condition. If the bit is high

the SCS pin will be enabled and used as a select pin.

Note that using the CSEN bit can be disabled or en-

abled via configuration option.

· MLS

This is the data shift select bit and is used to select

how the data is transferred, either MSB or LSB first.

Setting the bit high will select MSB first and low for

LSB first.

· CKEG and CKPOL

These two bits are used to setup the way that the

clock signal outputs and inputs data on the SPI bus.

These two bits must be configured before data trans-

fer is executed otherwise an erroneous clock edge

may be generated. The CKPOL bit determines the

base condition of the clock line, if the bit is high then

the SCK line will be low when the clock is inactive.

When the CKPOL bit is low then the SCK line will be

high when the clock is inactive. The CKEG bit deter-

mines active clock edge type which depends upon the

condition of CKPOL.

CKPOL

CKEG

SCK Clock Signal

High Base Level

Active Rising Edge

High Base Level

Active Falling Edge

Low Base Level

Active Falling Edge

Low Base Level

Active Rising Edge

SPI Communication

After the SPI interface is enabled by setting the SIMEN

bit high, then in the Master Mode, when data is written to

the SIMDR register, transmission/reception will begin si-

multaneously. When the data transfer is complete, the

TRF flag will be set automatically, but must be cleared

using the application program. In the Slave Mode, when

the clock signal from the master has been received, any

data in the SIMDR register will be transmitted and any

data on the SDI pin will be shifted into the SIMDR regis-

ter. The master should output an SCS signal to enable

the slave device before a clock signal is provided and

slave data transfers should be enabled/disabled be-

fore/after an SCS signal is received.

The SPI will continue to function even after a HALT in-

struction has been executed.

2C Interface

The I

2C interface is used to communicate with external

peripheral devices such as sensors, EEPROM memory

etc. Originally developed by Philips, it is a two line low

speed serial interface for synchronous serial data trans-

fer. The advantage of only two lines for communication,

relatively simple communication protocol and the ability

to accommodate multiple devices on the same bus has

made it an extremely popular interface type for many

applications.

2C Interface Operation

The I

2C serial interface is a two line interface, a serial

data line, SDA, and serial clock line, SCL. As many de-

vices may be connected together on the same bus, their

outputs are both open drain types. For this reason it is

necessary that external pull-high resistors are con-

nected to these outputs. Note that no chip select line ex-

ists, as each device on the I

2C bus is identified by a

unique address which will be transmitted and received

on the I

2C bus.

When two devices communicate with each other on the

bidirectional I

2C bus, one is known as the master device

and one as the slave device. Both master and slave can

transmit and receive data, however, it is the master de-

vice that has overall control of the bus. For these de-

vices, which only operates in slave mode, there are two

S T A R T s i g n a l

f r o m M a s t e r

S e n d s l a v e a d d r e s s

a n d R / W b i t f r o m M a s t e r

A c k n o w l e d g e

f r o m s l a v e

S e n d d a t a b y t e

f r o m M a s t e r

A c k n o w l e d g e

f r o m s l a v e

S T O P s i g n a l

f r o m M a s t e r

HT45R37 Datasheet(PDF) 44 Page - Holtek Semiconductor Inc

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