HT45R37 datasheet(68/100 Pages) HOLTEK

68 / 100 page

HT45R37

Rev. 1.10

January 29, 2010

time-out period may vary with temperature, VDD and

process variations. As the clear instruction only resets

the last stage of the divider chain, for this reason the ac-

tual division ratio and corresponding Watchdog Timer

time-out can vary by a factor of two. The exact division

ratio depends upon the residual value in the Watchdog

Timer counter before the clear instruction is executed.

If the fSYS/4 clock is used as the Watchdog Timer clock

source, it should be noted that when the system enters

the Power Down Mode, then the instruction clock is

stopped and the Watchdog Timer will lose its protecting

purposes. For systems that operate in noisy environ-

ments, using the 32K_INT RC oscillator is strongly rec-

ommended.

Under normal program operation, a Watchdog Timer

time-out will initialise a device reset and set the status bit

TO. However, if the system is in the Power Down Mode,

when a Watchdog Timer time-out occurs, the TO bit in

the status register will be set and only the Program

Counter and Stack Pointer will be reset. Three methods

can be adopted to clear the contents of the Watchdog

Timer. The first is an external hardware reset, which

means a low level on the RES pin, the second is using

the watchdog software instructions and the third is via a

²HALT² instruction.

Clearing the Watchdog Timer

There are two methods of using software instructions to

clear the Watchdog Timer, one of which must be chosen

by configuration option. The first option is to use the sin-

gle

²CLR WDT² instruction while the second is to use the

two commands

²CLR WDT1² and ²CLR WDT2². For the

first option, a simple execution of

²CLR WDT² will clear

the WDT while for the second option, both

²CLR WDT1²

and

²CLR WDT2² must both be executed to successfully

clear the Watchdog Timer. Note that for this second op-

tion, if

²CLR WDT1² is used to clear the Watchdog Timer,

successive executions of this instruction will have no ef-

fect, only the execution of a

²CLR WDT2² instruction will

clear the Watchdog Timer. Similarly after the

²CLR

WDT2

² instruction has been executed, only a successive

²CLR WDT1² instruction can clear the Watchdog Timer.

W D T S o u r c e

C o n f i g u r a t i o n

O p t i o n

C o n t r o l

L o g i c

C L R W D T 1 F l a g

C L R W D T 2 F l a g

1 o r 2 I n s t r u c t i o n s

f S Y S / 4

3 2 K _ I N T O s c i l l a t o r

8 - b i t D i v i d e r

f S

C L R

W D T T i m e - o u t

( 2 1 3 / f S , 2 1 4 / f S , 2 1 5 / f S o r 2 1 6 / f S )

¸ 2

7 - b i t P r e s c a l e r

f S / 2 8

f S / 2 1 2 , f S / 2 1 3 , f S / 2 1 4 o r f S / 2 1 5

C o n f i g O p t i o n

R T C O s c i l l a t o r

Watchdog Timer

M I S C R e g i s t e r

b 7

W D T E N 0

b 0

W D T E N 1

P A 0 ~ P A 3 O p e n D r a i n C o n t r o l

- d e s c r i b e d e l s e w h e r e

W a t c h d o g T i m e r E n a b l e C o n t r o l

O D E 0

W D T E N 3

W D T E N 2

W D T E N 3

O D E 1

O D E 2

O D E 3

W D T E N 2

W D T E N 1

W D T E N 0

d i s a b l e

e n a b l e

a l l o t h e r v a l u e s

Watchdog Timer Software Control

- MISC

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