HT45R37 datasheet(24/100 Pages) HOLTEK

24 / 100 page

HT45R37

Rev. 1.10

January 29, 2010

Timer/Event Counter will stop counting. If the Active

Edge Select bit is high, the Timer/Event Counter will be-

gin counting once a low to high transition has been re-

ceived on the external timer pin and stop counting when

the external timer pin returns to its original low level. As

before, the enable bit will be automatically reset to zero

and the Timer/Event Counter will stop counting. It is im-

portant to note that in the Pulse Width Measurement

Mode, the enable bit is automatically reset to zero when

the external control signal on the external timer pin re-

turns to its original level, whereas in the other two

modes the enable bit can only be reset to zero under

program control.

The residual value in the Timer/Event Counter, which

can now be read by the program, therefore represents

the length of the pulse received on the external timer

pin. As the enable bit has now been reset, any further

transitions on the external timer pin will be ignored. Not

until the enable bit is again set high by the program can

the timer begin further pulse width measurements. In

this way, single shot pulse measurements can be easily

Made.

It should be noted that in this mode the Timer/Event

Counter is controlled by logical transitions on the exter-

nal timer pin and not by the logic level. When the

Timer/Event Counter is full and overflows, an interrupt

signal is generated and the Timer/Event Counter will re-

load the value already loaded into the preload register

and continue counting. The interrupt can be disabled by

ensuring that the Timer/Event Counter Interrupt Enable

bit in the corresponding Interrupt Control Register, is re-

set to zero.

As the external timer pin is shared with an I/O pin, to en-

sure that the pin is configured to operate as a pulse

width measurement pin, two things have to happen. The

first is to ensure that the Operating Mode Select bits in

the Timer Control Register place the Timer/Event Coun-

ter in the Pulse Width Measurement Mode, the second

is to ensure that the port control register configures the

pin as an input.

Programmable Frequency Divider

- PFD

The Programmable Frequency Divider provides a

means of producing a variable frequency output suitable

for applications requiring a precise frequency generator.

The PFD output is pin-shared with the I/O pin PA3. The

PFD function is selected via configuration option, how-

ever, if not selected, the pin can operate as a normal I/O

pin.

The clock source for the PFD circuit can originate from

either Timer/Event Counter 0 or Timer/Event Counter 1

overflow signal selected via configuration option. The

output frequency is controlled by loading the required

values into the timer registers and prescaler registers to

give the required division ratio. The timer will begin to

count-up from this preload register value until full, at

which point an overflow signal is generated, causing the

PFD output to change state. The timer will then be auto-

matically reloaded with the preload register value and

continue counting-up.

+ 1

+ 2

+ 3

+ 4

T i m e r

E x t e r n a l T M R

P i n I n p u t

T n O N - w i t h T n E = 0

P r e s c a l e r O u t p u t

I n c r e m e n t

T i m e r C o u n t e r

Pulse Width Measure Mode Timing Chart

T i m e r O v e r f l o w

P F D C l o c k

P A 3 D a t a

P F D O u t p u t a t P A 3

PFD Output Control

HT45R37 Datasheet(PDF) 24 Page - Holtek Semiconductor Inc

HT45R37 Datasheet(HTML) 24 Page - Holtek Semiconductor Inc

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