8

DS895A2

CS4354

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE

12. Not all sample rates are supported for all clock ratios. See Section 4.2 “Sample Rate Range/Operational

Mode Detect” on page 13 for supported ratios and frequencies. SSM = Single-Speed Mode,

DSM = Double-Speed Mode, QSM = Quad-Speed Mode.

13. SCLK period is defined by the SCLK / LRCK ratio. The SCLK / LRCK ratio may be either 32, 48, or 64.

See Table 5 on page 14.

14.

Parameters

Symbol

Min

Typ

Max

Units

MCLK Frequency

7.6

-

55.3

MHz

MCLK Duty Cycle

45

-

55

%

Input Sample Rate

All MCLK/LRCK ratios combined

(Note 12)

(SSM) 256x, 384x, 512x, 768x, 1024x

(DSM) 128x, 192x, 256x, 384x, 512x

(QSM) 128x, 192x, 256x

Fs

30

30

84

170

-

-

-

-

216

54

108

216

kHz

kHz

kHz

kHz

External SCLK Mode

LRCK Duty Cycle

45

-

55

%

SCLK Pulse Width Low

20

-

-

ns

SCLK Pulse Width High

20

-

-

ns

SCLK Duty Cycle

45

-

55

%

SCLK rising to LRCK edge delay

20

-

-

ns

LRCK edge to SCLK rising delay

20

-

-

ns

SDIN valid to SCLK rising setup time

20

-

-

ns

SCLK rising to SDIN hold time

20

-

-

ns

Internal SCLK Mode

LRCK Duty Cycle

--

SCLK Period

(Note 13)

--

ns

MCLK falling to LRCK edge

-ns

LRCK edge to SCLK rising

-

(Note 14)

-ns

SDIN valid to SCLK rising setup time

--

ns

SCLK rising to SDIN hold time

MCLK / LRCK = 1024, 512, 256, 128

--

ns

MCLK / LRCK = 768, 384, 192

-

-

50%

1

2MCLK



----------------------------

–

50%

1

2MCLK



----------------------------

+

SCLK

----------------

–

4MCLK



---------------------------

4MCLK



---------------------------

512 Fs



----------------------- 10

+

512 Fs



----------------------- 15

+

384 Fs



----------------------- 15

+

tsclkr

tsclkw

2

-----------------

10

9

2MCLK



---------------------------tmclkf

++

=