68HC05CL48 datasheet(50/145 Pages) MOTOROLA

50 / 145 page

GENERAL RELEASE SPECIFICATION

June 11, 1997

MOTOROLA

INPUT/OUTPUT PORTS

MC68HC05CL48

7-2

REV 2.0

7.2

PORT A

Port A is an 8-bit bidirectional port. The port A data register is at $0000 and the

data direction register (DDRA) is at $0003. Reset does not affect the data register,

but clears the data direction register, thereby returning the ports to inputs. Writing

a one to a DDR bit sets the corresponding port bit to output mode. In addition to

normal I/O port function, PTA0-PTA2 are also used as additional external interrupt

inputs and PTA3-PTA7 are also associated with the KEYBOARD interrupt

function. See Section 4.3.2 for detail description on External and Keyboard

interrupts.

7.3

PORT B

Port B is an 8-bit bidirectional port. The port B data register is at $0001 and the

data direction register (DDRB) is at $0004. Reset does not affect the data register,

but clears the data direction register, thereby returning the ports to inputs. Writing

a one to a DDR bit sets the corresponding port bit to output mode.

7.4

PORT C

Port C is an 8-bit bidirectional port which shares its pins with subsystems A-2-D,

SPI and Timer under the control of the A-2-D status and control register ADCSR,

the SPI control register SPCR and the Timer pin conﬁguration register TIMCONF.

The port C data register is at $0002, the data direction register (DDRC) is at

$0005. Reset does not affect the data register, but clears the data direction,

thereby returning the ports to inputs. Writing a one to a DDR bit sets the

corresponding port bit to output mode. Writing a ‘1’ to the SPE-bit of the SPI

control register SPCR conﬁgures PTC[0:3] as dedicated SPI pins. Setting

CONF6-bit and CONF7-bit of the Timer pin conﬁguration register TIMCONF to ‘1’

conﬁgures PTC6 and PTC7 as Timer input capture pins respectively.

PTC[4:5] will always be available as IO port pins even after the ADON-bit is set.

When ADON-bit is set to ‘1’ and the CH[2:0] bits of the A-2-D status and control

ADON-bit is set to ‘1’ and the CH[2:0] bits of the A-2-D status and control register

is set to select channel-3, PTC[5] becomes an A-2-D input pin.

Table 7-1. summarizes the PORT C function when used as sub-system pins.

Table 7-2. PORT C I/O Conﬁguration

PORT C

I/O Mode

Sub-System Function

PTC0

Input

Output

SCK: SPI slave clock-in (MSTR = ‘0’, SPE=1).

SCK: SPI master clock-out (MSTR = ‘1’, SPE=1).

68HC05CL48 Datasheet(PDF) 50 Page - Motorola, Inc

68HC05CL48 Datasheet(HTML) 50 Page - Motorola, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL