68HC05CL48 datasheet(59/145 Pages) MOTOROLA

59 / 145 page

June 11, 1997

GENERAL RELEASE SPECIFICATION

MC68HC05CL48

TIMER

MOTOROLA

REV 2.0

8-7

8.1.2.2

Output Compare Register 2

The 16-bit output compare register 2 is made up of two 8-bit registers at locations

$17 (MSB) and $18 (LSB). The output compare register contents are compared

with the contents of the free-running counter once every four internal processor

clock cycles. If a match is found, the corresponding output compare ﬂag OC2F (bit

4 of timer status register $12) is set.

The output compare register values should be changed after each successful

comparison to establish a new elapsed time-out. An interrupt can also accompany

a successful output compare provided the corresponding interrupt enable bit

OC2IE (bit 4 of timer control register $11) is set.

After a processor write cycle to the output compare register containing the MSB

($17), the output compare function is inhibited until the LSB ($18) is also written.

The user must write both bytes (locations) if the MSB is written ﬁrst. A write made

only to the LSB ($18) will not inhibit the compare function. The free-running

counter is updated every four internal bus clock cycles. The minimum time

required to update the output compare register is a function of the program rather

than the internal hardware.

The processor can write to either byte of the output compare register without

affecting the other byte.

Because the output compare ﬂag OC2F and the output compare register 2 are

undetermined at power on, and are not affected by external reset, care must be

exercised when initializing the output compare function. A procedure as

recommended for Compare Register 1 should be followed.

76543210

OC2H

$0017

READ

OC2:15

OC2:14

OC2:13

OC2:12

OC2:11

OC2:10

OC2:9

OC2:8

WRITE

RESET

UUUUUUUU

76543210

OC2L

$0018

READ

OC2:7

OC2:6

OC2:5

OC2:4

OC2:3

OC2:2

OC2:1

OC2:0

WRITE

RESET

UUUUUUUU

68HC05CL48 Datasheet(PDF) 59 Page - Motorola, Inc

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