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68HC05CL48 Datasheet(PDF) 51 Page - Motorola, Inc |
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68HC05CL48 Datasheet(HTML) 51 Page - Motorola, Inc |
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51 / 145 page  June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 INPUT/OUTPUT PORTS MOTOROLA REV 2.0 7-3 PTC1 Input Output MISO: SPI slave data out (MSTR=0, SPE=1) MISO: SPI master data in (MSTR=1, SPE=1) PTC2 Input Output MOSI: SPI slave data in (MSTR=0, SPE=1) MOSI: SPI master data out (MSTR=1, SPE=1) PTC3 Input SS: SPI slave select signal (SPE=1) Note: This pin is internally connected to VDD when (MSTR=1), this means that PTC3 can be used as a normal port pin. PTC4 Input AD2: A-to-D input (ADON=1 and Channel-2 selected) PTC5 Input AD3: A-to-D input (ADON=1 and Channel-3 selected) PTC6 Input TCAP1: Timer input capture1 (CONF6=1). PTC7 Input TCAP2: Timer input capture2 (CONG7=1). Table 7-2. PORT C I/O Configuration PORT C I/O Mode Sub-System Function |
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