68HC05CL48 datasheet(20/145 Pages) MOTOROLA

20 / 145 page

GENERAL RELEASE SPECIFICATION

June 11, 1997

MOTOROLA

GENERAL DESCRIPTION

MC68HC05CL48

1-8

REV 2.0

when not used as I/O pins can be conﬁgured as two A-to-D pins, two Timer pins

and four SPI pins. See Section 7 for more details on the I/O ports.

1.4.10 SCK

This is the serial clock signal of the SPI. This pin can be conﬁgured as PTC0 pin

when the SPI function is not used.

1.4.11 MISO, MOSI

These are the master-in slave-out (MISO) and master-out slave-in (MOSI) data

pins for the SPI. These two pins can be conﬁgured as PTC1 and PTC2 pins

respectively when the SPI function is not used.

1.4.12 SS

This is the slave select pin for the SPI. This pin can be conﬁgured as PTC3 pin

when the SPI function is not used.

1.4.13 AD0-AD3

These four lines are the A/D inputs. AD2 and AD3 can be conﬁgured as PTC4 and

PTC5 pins respectively when not used as A-to-D inputs.

1.4.14 TCAP1

The TCAP1 input controls the input capture 1 feature of the on-chip programmable

timer system. Refer to Section 8 for additional information. This pin can be

conﬁgured as PTC6 pin when the timer input capture function is not used.

1.4.15 TCAP2

The TCAP2 input controls the input capture 2 feature of the on-chip programmable

timer system. Refer to Section 8 for additional information. This pin can be

conﬁgured as PTC7 pin when the timer input capture function is not used.

1.4.16 FSK+, FSK–

These two inputs are the non-inverting and inverting FSK signals respectively.

68HC05CL48 Datasheet(PDF) 20 Page - Motorola, Inc