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68HC05P9A Datasheet(PDF) 29 Page - Freescale Semiconductor, Inc |
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68HC05P9A Datasheet(HTML) 29 Page - Freescale Semiconductor, Inc |
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29 / 90 page ![]() GENERAL RELEASE SPECIFICATION INTERRUPTS Rev. 2.0 4-3 4.2 Timer Interrupt Three different timer interrupt flags cause a timer interrupt when they are set and enabled. The interrupt flags are in the timer status register (TSR), and the enable bits are in the timer control register (TCR). Any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory location $1FF8 and $1FF9. From RESET External Interrupt IRQ Internal Interrupt Timer I Bit Set Is Load PC From: IRQ: $1FFA-$1FFB Timer: $1FF8-$1FF9 Set I Bit Stack PC, X, A, CC Clear IRQ Request Latch Complete Interrupt Routine and Execute RTI Fetch Next Instruction Execute Instruction Y Y Y N N N Figure 4-1. Hardware Interrupt Flowchart Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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