68HC05P9A datasheet(41/90 Pages) FREESCALE

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GENERAL RELEASE SPECIFICATION

SIMPLE SERIAL INPUT/OUTPUT PORT

Rev. 2.0

7-3

7.2

SIOP Registers

The following paragraphs describe the SIOP registers.

7.2.1 SIOP Control Register (SCR)

This register is located at address $000A and contains two bits.

SPE — Serial Peripheral Enable

When set, this bit enables the serial I/O port and initializes the port B DDR such

that PB5 (SDO) is output, PB6 (SDI) is input and PB7 (SCK) is input (slave

mode only). The port B DDR can be altered subsequently as the application

requires and the port B data register (except for PB5) can be manipulated as

usual. However, these actions could affect the transmitted or received data.

When SPE is cleared, port B reverts to standard parallel I/O without affecting

the port B data register or DDR. SPE is readable and writable any time but

clearing SPE while a transmission is in progress will abort the transmission,

reset the bit counter, and return port B to its normal I/O function. Reset clears

this bit.

MSTR — Master Mode

When set, this bit conﬁgures the SIOP for master mode. This means that the

transmission is initiated by a write to the data register and the SCK pin

becomes an output providing a synchronous data clock at a ﬁxed rate of E (bus

clock) divided by four. While the device is in master mode, the SDO and SDI

pins do not change function. These pins behave exactly as they would in slave

mode.

Reset clears this bit and conﬁgures the SIOP for slave operation.

MSTR may be set at any time regardless of the state of SPE. Clearing MSTR

will abort any transmission in progress.

$0A

SPE

MSTR

0000

RESET:

00000000

Figure 7-3. SIOP Control Register

Freescale Semiconductor, Inc.

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68HC05P9A Datasheet(PDF) 41 Page - Freescale Semiconductor, Inc