68HC05P9A datasheet(33/90 Pages) FREESCALE

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GENERAL RELEASE SPECIFICATION

RESETS

Rev. 2.0

5-1

SECTION 5

RESETS

The MCU can be reset three ways: by the initial power-on reset function, by an

active low input to the RESET pin, and by a computer operating properly (COP)

watchdog-timer timeout.

5.1

Power-On Reset (POR)

An internal reset is generated on power-up to allow the internal clock generator to

stabilize. The power-on reset is strictly for power turn-on conditions and should

not be used to detect a drop in the power supply voltage.

There is a 4064 internal processor clock cycle (tcyc) oscillator stabilization delay

after the oscillator becomes active. If the RESET pin is low at the end of this 4064-

cycle delay, the MCU will remain in the reset condition until RESET goes high.

5.2

RESET Pin

The MCU is reset when a logic zero is applied to the RESET input for a period of

one and one-half machine cycles (t

cyc).

5.3

Computer Operating Properly (COP) Reset

The MCU contains a watchdog timer that automatically times out if not reset

(cleared) within a speciﬁc time by a program reset sequence.

If the COP

watchdog timer is allowed to time-out, an internal reset is generated to reset the

MCU. Because the internal RESET signal is used, the MCU comes out of a COP

reset in the same operating mode it was in when the COP time-out was

generated.

The COP reset function is enabled or disabled by a mask option.

Refer to SECTION 9 COMPUTER OPERATING PROPERLY (COP) for more

information on the COP.

Freescale Semiconductor, Inc.

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Go to: www.freescale.com

68HC05P9A Datasheet(PDF) 33 Page - Freescale Semiconductor, Inc