68HC05P9A datasheet(82/90 Pages) FREESCALE

82 / 90 page

GENERAL RELEASE SPECIFICATION

ELECTRICAL SPECIFICATIONS

MC68HC05P9A

13-8

Rev. 2.0

Figure 13-4. Power-On Reset Timing

Figure 13-5. External Reset Timing

SC1 PIN

VDD

4064

tcyc

INTERNAL

CLOCK

INTERNAL

ADDRESS

BUS

INTERNAL

DATA

BUS

1FFF

1FFE

NEW

PCL

NEW

PCH

1FFE

1. Internal clock, internal address bus, and internal data bus signals are not available externally.

2. An internal PO R reset is triggered as V

rises through a threshold (typically 1-2 V).

VDD THRESHOLD (TYPICALLY 1-2 V)

t VDDR

NOTES:

NTERNAL

CLOCK

NTERNAL

DDRESS

BUS

RESET

NOTES:

1. Internal clock, internal address bus, and internal data bus signals are not available externally.

2. The next rising edge of t he internal processor clock after t he rising edge of RESET initiates the reset sequence.

tRL

NEW PC

DUMMY

NTERNAL

DATA

BUS

NEW PC

CODE

1FFF

NEW

PCL

1FFE

NEW

PCH

1FFE

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

68HC05P9A Datasheet(PDF) 82 Page - Freescale Semiconductor, Inc

68HC05P9A Datasheet(HTML) 82 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

Datasheet Download

Link URL