68HC705SB7 datasheet(49/170 Pages) FREESCALE

49 / 170 page

August 27, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05SB7

LOW POWER MODES

MOTOROLA

REV 2.1

6-5

To put the MCU in the data retention mode:

Drive the RESET pin to a logic zero.

Lower the VDD voltage. The RESET pin must remain low continuously

during data retention mode.

To take the MCU out of the data retention mode:

Return VDD to normal operating voltage.

Return the RESET pin to a logic one.

6.4

SLOW MODE

The Slow Mode feature permits a slow down of all the internal operations and thus

reduces power consumption. It is particularly useful while going to the WAIT

mode. Slow mode is enabled by setting the SCLK bit in the Miscellaneous Control

SCLK — Slow Clock

Setting this bit to one will slow down the internal oscillator. Setting this bit to

zero the system will run at the nominal bus speed (fosc/2). This bit is cleared

during power-on or external reset.

1 =

Slow clock selected:

Internal operating frequency, fOP=fBUS=fOSC/1600.

0 =

Normal clock selected:

Internal operating frequency, fOP=fBUS=fOSC/2.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

MCR

TSEN

LVRON

SCLK

CSSEL

TCSEL

ESVEN

SMINLEV

$000B

COPON

reset:

01000000

U = UNAFFECTED BY RESET

Figure 6-2. Miscellaneous Control Register (MCR)

68HC705SB7 Datasheet(PDF) 49 Page - Freescale Semiconductor, Inc

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