MPC8360E datasheet(30/108 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

Freescale Semiconductor

UCC Ethernet Controller: Three-Speed Ethernet, MII Management

Figure 10 shows the GMII transmit AC timing diagram.

Figure 10. GMII Transmit AC Timing Diagram

8.2.1.2

GMII Receive AC Timing Specifications

Table 28 provides the GMII receive AC timing specifications.

GTX_CLK clock fall time, (80% to 20%)

tGTXF

——

1.0

—

GTX_CLK125 clock period

tG125

—8.0

—

GTX_CLK125 reference clock duty cycle measured at

LVDD/2

tG125H/tG125

—

Notes:

1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs

and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII transmit timing

(GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching

the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect to the tGTX clock

reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in

general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.

For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is

used with the appropriate letter: R (rise) or F (fall).

2. This symbol is used to represent the external GTX_CLK125 signal and does not follow the original symbol naming

convention.

3. In rev. 2.0 silicon, due to errata, tGTKHDX minimum and tGTKHDV maximum are not supported when the GTX_CLK is selected.

Refer to Errata

QE_ENET18 in Chip Errata for the MPC8360E, Rev. 1.

Table 28. GMII Receive AC Timing Specifications

At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Notes

RX_CLK clock period

tGRX

—8.0

—

RX_CLK duty cycle

tGRXH/tGRX

—

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK

tGRDVKH

2.0

—

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK

tGRDXKH

0.2

—

RX_CLK clock rise time, (20% to 80%)

tGRXR

——

1.0

—

Table 27. GMII Transmit AC Timing Specifications (continued)

At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Notes

GTX_CLK

TXD[7:0]

tGTKHDX

tGTX

tGTXH

tGTXR

tGTXF

TX_EN

TX_ER

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