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MPC8360E Datasheet(PDF) 65 Page - Freescale Semiconductor, Inc |
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MPC8360E Datasheet(HTML) 65 Page - Freescale Semiconductor, Inc |
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65 / 108 page  MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4 Freescale Semiconductor 65 HDLC, BISYNC, Transparent, and Synchronous UART 19.2 HDLC, BISYNC, Transparent, and Synchronous UART AC Timing Specifications Table 62 and Table 63 provide the input and output AC timing specifications for HDLC, BISYNC, transparent, and synchronous UART protocols. Table 62. HDLC, BISYNC, and Transparent AC Timing Specifications1 Characteristic Symbol2 Min Max Unit Outputs—Internal clock delay tHIKHOV 0 11.2 ns Outputs—External clock delay tHEKHOV 1 10.8 ns Outputs—Internal clock high impedance tHIKHOX -0.5 5.5 ns Outputs—External clock high impedance tHEKHOX 18 ns Inputs—Internal clock input setup time tHIIVKH 8.5 — ns Inputs—External clock input setup time tHEIVKH 4— ns Inputs—Internal clock input hold time tHIIXKH 1.4 — ns Inputs—External clock input hold time tHEIXKH 1— ns Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). Table 63. Synchronous UART AC Timing Specifications1 Characteristic Symbol2 Min Max Unit Outputs—Internal clock delay tUAIKHOV 0 11.3 ns Outputs—External clock delay tUAEKHOV 114 ns Outputs—Internal clock high impedance tUAIKHOX 011 ns Outputs—External clock high impedance tUAEKHOX 114 ns Inputs—Internal clock input setup time tUAIIVKH 6— ns Inputs—External clock input setup time tUAEIVKH 8— ns Inputs—Internal clock input hold time tUAIIXKH 1— ns Inputs—External clock input hold time tUAEIXKH 1— ns Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). |
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