MPC8360E datasheet(49/108 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

Freescale Semiconductor

JTAG

10.2

JTAG AC Electrical Characteristics

This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the device.

Table 43 provides the JTAG AC timing specifications as defined in Figure 30 through Figure 33.

Table 43. JTAG AC Timing Specifications (Independent of CLKIN)1

At recommended operating conditions (see Table 2).

Parameter

Symbol 2

Min

Max

Unit

Notes

JTAG external clock frequency of operation

fJTG

33.3

MHz

—

JTAG external clock cycle time

tJTG

—

JTAG external clock duty cycle

tJTKHKL/tJTG

—

JTAG external clock rise and fall times

tJTGR & tJTGF

—

TRST assert time

tTRST

—

Input setup times:

Boundary-scan data

TMS, TDI

tJTDVKH

tJTIVKH

—

Input hold times:

Boundary-scan data

TMS, TDI

tJTDXKH

tJTIXKH

—

Valid times:

Boundary-scan data

TDO

tJTKLDV

tJTKLOV

Output hold times:

Boundary-scan data

TDO

tJTKLDX

tJTKLOX

—

JTAG external clock to output high impedance:

Boundary-scan data

TDO

tJTKLDZ

tJTKLOZ

5, 6

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.

The output timings are measured at the pins. All output timings assume a purely resistive 50-

Ω load (see Figure 22).

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG

device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock

reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time

data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general,

the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise

and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

4. Non-JTAG signal input timing with respect to tTCLK.

5. Non-JTAG signal output timing with respect to tTCLK.

6. Guaranteed by design and characterization.

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