MPC8360E datasheet(6/108 Pages) FREESCALE

6 / 108 page

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

Freescale Semiconductor

Overview

— Implements the Rinjdael symmetric key cipher

— Key lengths of 128, 192, and 256 bits, two key

– ECB, CBC, CCM, and counter modes

— ARC four execution unit (AFEU)

–

Implements a stream cipher compatible with the RC4 algorithm

–

40- to 128-bit programmable key

— Message digest execution unit (MDEU)

– SHA with 160-, 224-, or 256-bit message digest

– MD5 with 128-bit message digest

– HMAC with either SHA or MD5 algorithm

— Random number generator (RNG)

— Four crypto-channels, each supporting multi-command descriptor chains

–

Static and/or dynamic assignment of crypto-execution units via an integrated controller

–

Buffer size of 256 bytes for each execution unit, with flow control for large data sizes

— Storage/NAS XOR parity generation accelerator for RAID applications

•

Dual DDR SDRAM memory controllers on the MPC8360E and a single DDR SDRAM memory

controller on the MPC8358E

— Programmable timing supporting both DDR1 and DDR2 SDRAM

— On the MPC8360E, the DDR buses can be configured as two 32-bit buses or one 64-bit bus;

on the MPC8358E, the DDR bus can be configured as a 32- or 64-bit bus

— 32- or 64-bit data interface, up to 333 MHz (for the MPC8360E) and 266 MHz (for the

MPC8358E) data rate

— Four banks of memory, each up to 1 Gbyte

— DRAM chip configurations from 64 Mbits to 1 Gigabit with ×8/×16 data ports

— Full ECC support (when the MPC8360E is configured as 2×32-bit DDR memory controllers,

both support ECC)

— Page mode support (up to 16 simultaneous open pages for DDR1, up to 32 simultaneous open

pages for DDR2)

— Contiguous or discontiguous memory mapping

— Read-modify-write support

— Sleep mode support for self refresh SDRAM

— Supports auto refreshing

— Supports source clock mode

— On-the-fly power management using CKE

— Registered DIMM support

— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2

— External driver impedance calibration

— On-die termination (ODT)

MPC8360E Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc

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