MPC8360E datasheet(91/108 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

Freescale Semiconductor

Clocking

22.2

Core PLL Configuration

RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300

core clock (core_clk). Table 73 shows the encodings for RCWL[COREPLL]. COREPLL values not listed

in Table 73 should be considered reserved.

High

0110

6:1

200

High

0111

7:1

233

High

1000

8:1

High

1001

9:1

High

1010

10:1

High

1011

11:1

High

1100

12:1

High

1101

13:1

High

1110

14:1

High

1111

15:1

High

0000

16:1

1 CFG_CLKIN_DIV is only used for host mode; CLKIN must be tied low and CFG_CLKIN_DIV must be pulled down (low) in

agent mode.

2 CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.

Table 73. e300 Core PLL Configuration

RCWL[COREPLL]

core_clk:csb_clk

Ratio

VCO divider

0–1

2–5

0000

PLL bypassed

(PLL off,

csb_clk

clocks core directly)

PLL bypassed

(PLL off,

csb_clk

clocks core directly)

0001

01:1

÷2

0001

01:1

÷4

0001

01:1

÷8

0001

01:1

÷8

0001

11.5:1

÷2

0001

11.5:1

÷4

0001

11.5:1

÷8

Table 72. CSB Frequency Options (continued)

CFG_CLKIN_DIV

at Reset1

SPMF

csb_clk:

Input Clock Ratio2

Input Clock Frequency (MHz)2

16.67

33.33

66.67

csb_clk Frequency (MHz)

MPC8360E Datasheet(PDF) 91 Page - Freescale Semiconductor, Inc

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