BTS6480SF datasheet(11/73 Pages) INFINEON

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SPOC - BTS6480SF

Electrical Characteristics

Data Sheet

Rev. 1.0, 2010-04-12

Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are

not designed for continuous repetitive operation.

4.1.20 Current through serial output pin SO

-2.0

2.0

≤ 2min.

PWM Clock and Sense Synchronization Pin

4.1.21 Voltage at PWM clock input pin

PCLK

-0.3

DD + 0.3 V

–

4.1.22 Current through PWM clock input pin

PLCK

-0.75

-2.0

0.75

2.0

mA –

≤ 2min.

4.1.23 Voltage at sense synchronization pin

ISSY

-0.3

DD + 0.3 V

–

4.1.24 Current through sense synchronization pin

ISSY

-2.0

2.0

≤ 2min.

Limp Home Pin

4.1.25 Voltage at limp home input pin

LHI

-0.3

5.5

–

4.1.26 Current through limp home input pin

LHI

-0.75

-2.0

0.75

2.0

mA –

≤ 2min.

External Driver Pins

4.1.27 Voltage at external driver output

EDO

-0.3

DD + 0.3 V

–

4.1.28 Current through external driver output

EDO

-1.0

1.0

≤ 2min.

4.1.29 Voltage at external driver diagnosis enable

EDD

-0.3

DD + 0.3 V

–

4.1.30 Current through external driver diagnosis enable

EDD

-1.0

1.0

≤ 2min.

Temperatures

4.1.31 Junction temperature

-40

150

°C–

4.1.32 Dynamic temperature increase while switching

∆Tj

–60

–

4.1.33 Storage temperature

stg

-55

150

°C–

ESD Susceptibility

4.1.34 ESD susceptibility HBM

OUT pins vs. VBB

other pins incl. OUT vs. GND

ESD

-4

-2

HBM 7)

–

1) Not subject to production test, specified by design.

2) Device is mounted on an FR4 2s2p board according to Jedec JESD51-2,-5,-7 at natural convection; The product

(chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu).

Where applicable, a thermal via array under the package contacted the first inner copper layer.

3) In accordance to AEC Q100-012 and AEC Q101-006.

4) RI is the internal resistance of the load dump pulse generator.

5) Over current protection is a protection feature. Operation in over current protection is considered as “outside” normal

operating range. Protection features are not designed for continuous repetitive operation.

6) Pulse shape represents inductive switch off: ID(t) = ID(0) × (1 - t / tpulse); 0 < t < tpulse

7) ESD resistivity, HBM according to EIA/JESD 22-A 114B (1.5 k

Ω, 100 pF)

Absolute Maximum Ratings (cont’d)1)

j = -40 to +150 °C; all voltages with respect to ground

(unless otherwise specified)

Pos.

Parameter

Symbol

Limit Values

Unit Conditions

min.

max.

BTS6480SF Datasheet(PDF) 11 Page - Infineon Technologies AG

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