HT45F43 datasheet(41/152 Pages) HOLTEK

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Operation Mode

Description

CPU

fSYS

fSUB

fTBC

NORMAL Mode

fH~fH/64

SLOW Mode

IDLE0 Mode

Off

On/Off

IDLE1 Mode

Off

SLEEP0 Mode

Off

SLEEP1 Mode

Off

· NORMAL Mode

As the name suggests this is one of the main operating modes where the microcontroller has all of its

functions operational and where the system clock is provided by one of the high speed oscillators.

This mode operates allowing the microcontroller to operate normally with a clock source will come

from one of the high speed oscillators, either the HXT, ERC, HIRC or EC oscillators. The high speed

oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected

by the CKS2~CKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is

used, running the microcontroller at a divided clock ratio reduces the operating current.

· SLOW Mode

This is also a mode where the microcontroller operates normally although now with a slower speed

clock source. The clock source used will be from one of the low speed oscillators, either the LXT or

the LIRC. Running the microcontroller in this mode allows it to run with much lower operating

currents. In the SLOW Mode, the fH is off.

· SLEEP0 Mode

The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the

SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the fSUB and fS clocks will

be stopped too, and the Watchdog Timer function is disabled. In this mode, the LVDEN is must set to

²0². If the LVDEN is set to ²1²,itwon¢t enter the SLEEP0 Mode.

· SLEEP1 Mode

The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the

SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However the fSUB and fS

clocks will continue to operate if the LVDEN is

²1² or the Watchdog Timer function is enabled and if

its clock source is chosen via configuration option to come from the fSUB.

· IDLE0 Mode

The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the

SMOD register is high and the FSYSON bit in the WDTC register is low. In the IDLE0 Mode the

system oscillator will be inhibited from driving the CPU but some peripheral functions will remain

operational such as the Watchdog Timer, Time Base 0 and SIM. In the IDLE0 Mode, the system

oscillator will be stopped. In the IDLE0 Mode the Watchdog Timer clock, fS, will either be on or off

depending upon the fS clock source. If the source is fSYS/4 then the fS clock will be off, and if the

source comes from fSUB then fS will be on.

· IDLE1 Mode

The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the

SMOD register is high and the FSYSON bit in the WDTC register is high. In the IDLE1 Mode the

system oscillator will be inhibited from driving the CPU but may continue to provide a clock source

to keep some peripheral functions operational such as the Watchdog Timer, Time Base 0 and SIM. In

the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high

speed or low speed system oscillator. In the IDLE1 Mode the Watchdog Timer clock, fS, will be on.

If the source is fSYS/4 then the fS clock will be on, and if the source comes from fSUB then fS will be on.

HT45F23/HT45F43

8-Bit Flash MCU with Op Amps & Comparators

Rev. 1.20

September 15, 2011

HT45F43 Datasheet(PDF) 41 Page - Holtek Semiconductor Inc

HT45F43 Datasheet(HTML) 41 Page - Holtek Semiconductor Inc

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