HT67F60 datasheet(129/242 Pages) HOLTEK

129 / 242 page

HT67F30/HT67F40/HT67F50/HT67F60

TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM

Rev. 1.50

128

March 06 , 2012

Rev. 1.50

129

March 06 , 2012

Counter Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

TM O/P Pin

(TnOC=1)

Time

Counter stopped

by CCRA

Pause

Resume

Counter Stops

by software

Counter Reset when

TnON returns high

TnM [1:0] = 10 ; TnIO [1:0] = 11

Pulse Width

set by CCRA

Output Inverts

when TnPOL = 1

No CCRP Interrupts

generated

TM O/P Pin

(TnOC=0)

TCKn pin

Software

Trigger

Cleared by

CCRA match

TCKn pin

Trigger

Auto. set by

TCKn pin

Software

Trigger

Software

Clear

Software

Trigger

Software

Trigger

Single Pulse Mode

Note: 1. Counter stopped by CCRA

2. CCRP is not used

3. The pulse is triggered by the TCKn pin or by setting the TnON bit high

4. A TCKn pin active edge will automatically set the TnON bit hight

5. In the Single Pulse Mode, TnIO [1:0] must be set to “11” and can not be changed.

However a compare match from Comparator A will also automatically clear the TnON bit and thus

generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the

pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter can

only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the

Single Pulse Mode CCRP is not used. The TnCCLR and TnDPX bits are not used in this Mode.

Capture Input Mode

To select this mode bits TnM1 and TnM0 in the TMnC1 register should be set to 01 respectively.

This mode enables external signals to capture and store the present value of the internal counter and

can therefore be used for applications such as pulse width measurements. The external signal is

supplied on the TPn_0 or TPn_1 pin, whose active edge can be either a rising edge, a falling edge or

both rising and falling edges; the active edge transition type is selected using the TnIO1 and TnIO0

bits in the TMnC1 register. The counter is started when the TnON bit changes from low to high

which is initiated using the application program.

When the required edge transition appears on the TPn_0 or TPn_1 pin the present value in the

counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what

events occur on the TPn_0 or TPn_1 pin the counter will continue to free run until the TnON bit

changes from high to low. When a CCRP compare match occurs the counter will reset back to zero;

in this way the CCRP value can be used to control the maximum counter value. When a CCRP

compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the

number of overflow interrupt signals from the CCRP can be a useful method in measuring long

pulse widths. The TnIO1 and TnIO0 bits can select the active trigger edge on the TPn_0 or TPn_1

pin to be a rising edge, falling edge or both edge types. If the TnIO1 and TnIO0 bits are both set

high, then no capture operation will take place irrespective of what happens on the TPn_0 or TPn_1

pin, however it must be noted that the counter will continue to run.

HT67F60 Datasheet(PDF) 129 Page - Holtek Semiconductor Inc

HT67F60 Datasheet(HTML) 129 Page - Holtek Semiconductor Inc

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