HT66F016 datasheet(70/116 Pages) HOLTEK

70 / 116 page

HT66F016/HT66F017/HT68F016/HT68F017

Rev. 1.00

May 14, 2012

· 16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=0

CCRP

1~255

Period

CCRP

´ 256

65536

Duty

CCRA

If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 2 and CCRA =128

The STM PWM output frequency = (fSYS/4)/(2

´256) = fSYS/2048 = 7.8125kHz, duty = 128 / (2´256) = 25%.

If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty

is 100%.

· 16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=1

CCRP

1~255

Period

CCRA

Duty

CCRP

´ 256

65536

The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cy-

cle is defined by the (CCRP

´256) except when the CCRP value is equal to 0.

Counter Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

TM O/P Pin

(TnOC=1)

Time

Counter cleared

by CCRA

Pause Resume

Counter Stop if

TnON bit low

Counter Reset when

TnON returns high

TnDPX = 1; TnM [1:0] = 10

PWM Duty Cycle

set by CCRP

PWM resumes

operation

Output controlled by

other pin-shared function

Output Inverts

when TnPOL = 1

PWM Period

set by CCRA

TM O/P Pin

(TnOC=0)

PWM Mode -- TnDPX = 1

Note:

1. Here TnDPX=1 -- Counter cleared by CCRA

2. A counter clear sets the PWM Period

3. The internal PWM function continues running even when TnIO [1:0] = 00 or 01

4. The TnCCLR bit has no influence on PWM operation

HT66F016 Datasheet(PDF) 70 Page - Holtek Semiconductor Inc

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