TLV5614EP

2.7V TO 5.5V 12BIT 3 µs QUADRUPLE DIGITALTOANALOG CONVERTER

WITH POWER DOWN

SGLS355 − JUNE 2006

2

POST OFFICE BOX 655303

description (continued)

The resistor string output voltage is buffered by a 2

× gain rail-to-rail output buffer. The buffer features a Class AB

output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode

makes it ideal for single-voltage, battery-based applications. The settling time of the DAC is programmable to

allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits

within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD

terminals to reduce the need for a low source-impedance drive to the terminal. REFINAB and REFINCD allow

DAC A and B to have a different reference voltage than DAC C and D.

The TLV5614 is implemented with a CMOS process and is available in a 16-terminal TSSOP package. The

TLV5614M is characterized for operation from −55

°C to 125°C.

AVAILABLE OPTIONS

TA

PACKAGE

TA

TSSOP (PW)

−55

°C to 125°C

TLV5614MPWREP