WM8533 datasheet(20/41 Pages) WOLFSON

20 / 41 page

WM8533

Production Data

PD, July 2012, Rev 4.0

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

Figure 16 Left Justified Audio Interface (assuming n-bit word length)

In I

2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.

The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and

the MSB of the next.

Figure 17 I

2S Justified Audio Interface (assuming n-bit word length)

In DSP mode, the left channel MSB is available on either the 1

st (mode B) or 2nd (mode A) rising edge

of BCLK (selectable by AIF_LRCLK_INV) following a rising edge of LRCLK. Right channel data

immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,

there may be unused BCLK cycles between the LSB of the right channel data and the next sample.

In device master mode, the LRCLK output will resemble the frame pulse shown in Figure 18 and

Figure 19. In device slave mode, Figure 20 and Figure 21, it is possible to use any length of frame

pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK

period before the rising edge of the next frame pulse.

Figure 18 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Master)

WM8533 Datasheet(PDF) 20 Page - Wolfson Microelectronics plc