WM8533 datasheet(22/41 Pages) WOLFSON

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WM8533

Production Data

PD, July 2012, Rev 4.0

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3 (03h)

AIF_CTRL1

AIF_MSTR

Master/Slave Select

0 = Slave

1 = Master

R4 (04h)

AIF_CTRL2

5:3

AIF_BCLKD

IV [2:0]

000

BCLK Divider Control (Master Mode)

000 = MCLK/4

001 = MCLK/8

010 = 32fs

011 = 64fs

100 = 128fs

101 to 111 = Reserved

2:0

AIF_SR

[2:0]

000

MCLK:LRCLK Ratio

000 = Auto detect

001 = 128fs

010 = 192fs

011 = 256fs

100 = 384fs

101 = 512fs

110 = 768fs

111 = 1152fs

Table 9 DAC Clocking Mode Control

Interface timing is such that the input data and left/right clock are sampled on the rising edge of

BCLK. By setting the appropriate BCLK and LRCLK polarity bits, the WM8533 DAC can sample data

on the opposite clock edges.

The control of audio interface formats and clock polarities is summarised in Table 10.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3 (03h)

AIF_CTRL1

AIF_LRCLK

_INV

LRCLK Inversion Control

0 = Normal polarity

1 = Inverted polarity

When AIF_FMT [1:0]=11 (DSP Mode):

0 = Mode A (2nd clock)

1 = Mode B (1st clock)

AIF_BCLK_

INV

BCLK Inversion Control

Slave mode:

0 = use rising edge

1 = use falling edge

Master mode:

0 = BCLK normal

1 = BCLK inverted

4:3

AIF_WL

[1:0]

Audio Data Word Length

00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits

1:0

AIF_FMT

[1:0]

Audio Data Interface Format

00 = Right justified

01 = Left justified

10 = I2S format

11 = DSP mode

Table 10 Audio Interface Control

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