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WM8956CGEFL/V Datasheet(PDF) 42 Page - Wolfson Microelectronics plc

Part # WM8956CGEFL/V
Description  Hi-Fi DAC with 1W Stereo Class D Speaker Drivers and Headphone Drivers
PDF  80 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8956CGEFL/V Datasheet(HTML) 42 Page - Wolfson Microelectronics plc

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WM8956
Production Data
w
PD, November 2011, Rev 4.1
42
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R9 (09h)
Audio
Interface (2)
6
ALRCGPIO
0
GPIO1 Pin Function Select
0 = GPIO1 pin disabled
1 = GPIO1 pin configured as GPIO
R48 (30h)
Additional
Control (4)
6:4
GPIOSEL
[2:0]
000
GPIO1 GPIO Function Select:
000 = Jack detect input
001 = Reserved
010 = Temperature ok
011 = Debounced jack detect output
100 = SYSCLK output
101 = PLL lock
110 = Logic 0
111 = Logic 1
7
GPIOPOL
0
GPIO Polarity Invert
0 = Non inverted
1 = Inverted
R52 (34h)
Clocking (2)
8:6
OPCLKDIV
[2:0]
000
SYSCLK Output to GPIO Clock Division
Ratio
000 = SYSCLK
001 = SYSCLK / 2
010 = SYSCLK / 3
011 = SYSCLK / 4
100 = SYSCLK / 5.5
101 = SYSCLK / 6
Table 26 GPIO Control
Slow clock must be enabled (TOEN = 1) when using the jack detect function. This slow clock is used
to debounce the jack detect input. The debounce period can be selected using TOCLKSEL.
The temperature sensor must be enabled for the "Temperature ok" GPIO output to function properly.
For further details of the Jack detect operation see the Headphone Switch section.
DIGITAL AUDIO INTERFACE
The digital audio interface is used for inputting DAC data into the WM8956. It uses three pins:
DACDAT: DAC data input
DACLRC: DAC data alignment clock
BCLK: Bit clock, for synchronisation
The clock signals BCLK and DACLRC can be outputs when the WM8956 operates as a master, or
inputs when it is a slave (see Master and Slave Mode Operation, below).
Four different audio data formats are supported:
Left justified
Right justified
I
2S
DSP mode
All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8956 can be configured as either a master or slave mode device. As a master device the
WM8956 generates BCLK and DACLRC and thus controls sequencing of the data transfer on
DACDAT. In slave mode, the WM8956 responds with data to clocks it receives over the digital audio
interface. The mode can be selected by writing to the MS bit. Master and slave modes are illustrated
below.



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