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WM8956CGEFL/V Datasheet(PDF) 48 Page - Wolfson Microelectronics plc |
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WM8956CGEFL/V Datasheet(HTML) 48 Page - Wolfson Microelectronics plc |
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48 / 80 page ![]() WM8956 Production Data w PD, November 2011, Rev 4.1 48 Setting the WL8 register bit allows the device to operate with 8-bit data. In this mode it is possible to use 8 BCLK cycles per LRC frame. When using DSP mode B, this allows 8-bit data words to be output consecutively every 8 BCLK cycles and can be used with 8-bit data words using the A-law and u-law companding functions. BIT7 BIT[6:4] BIT[3:0] SIGN EXPONENT MANTISSA Table 30 8-bit Companded Word Composition u-law Companding 0 20 40 60 80 100 120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Normalised Input 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Figure 32 µ-Law Companding A-law Companding 0 20 40 60 80 100 120 0 0.2 0.4 0.6 0.8 1 Normalised Input 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Figure 33 A-Law Companding |
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