WM8988 datasheet(12/56 Pages) WOLFSON

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WM8988

Production Data

PD, Rev 4.0, October 2008

Test Conditions

DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25

oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless

otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Bit Clock Timing Information

BCLK rise time (10pF load)

tBCLKR

BCLK fall time (10pF load)

tBCLKF

BCLK duty cycle (normal mode, BCLK = MCLK/n)

tBCLKDS

50:50

BCLK duty cycle (USB mode, BCLK = MCLK)

tBCLKDS

TMCLKDS

Audio Data Input Timing Information

DACLRC propagation delay from BCLK falling edge

tDL

ADCDAT propagation delay from BCLK falling edge

tDDA

DACDAT setup time to BCLK rising edge

tDST

DACDAT hold time from BCLK rising edge

tDHT

AUDIO INTERFACE TIMING – SLAVE MODE

Figure 3 Digital Audio Data Timing – Slave Mode

Test Conditions

DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25

oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless

otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

tBCY

BCLK pulse width high

tBCH

BCLK pulse width low

tBCL

DACLRC set-up time to BCLK rising edge

tLRSU

DACLRC hold time from BCLK rising edge

tLRH

DACDAT hold time from BCLK rising edge

tDH

ADCDAT propagation delay from BCLK falling edge

tDD

Note:

BCLK period should always be greater than or equal to MCLK period.

BCLK

LRC

BCH

BCL

BCY

DACDAT

ADCDAT

LRSU

LRH

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