WM8988 datasheet(18/56 Pages) WOLFSON

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WM8988

Production Data

PD, Rev 4.0, October 2008

MONO MIXING

The stereo ADC can operate as a stereo or mono device, or the two channels can be mixed to mono,

either in the analogue domain (i.e. before the ADC) or in the digital domain (after the ADC).

MONOMIX selects the mode of operation. For analogue mono mix either the left or right channel

ADC can be used, allowing the unused ADC to be powered off or used for a dc measurement

conversion. The user also has the flexibility to select the data output from the audio interface using

DATSEL. The default is for left and right channel ADC data to be output, but the interface may also

be configured so that e.g. left channel ADC data is output as both left and right data for when an

analogue mono mix is selected.

Note:

If DC measurement is selected this overrides the MONOMIX selection.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R31 (1Fh)

ADC input

Mode

7:6

MONOMIX

[1:0]

00: Stereo

01: Analogue Mono Mix (using left ADC)

10: Analogue Mono Mix (using right ADC)

11: Digital Mono Mix

Table 7 Mono Mixing

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R23 (17h)

Additional

Control (1)

3:2

DATSEL

[1:0]

00: left data=left ADC; right data =right ADC

01: left data =left ADC; right data = left ADC

10: left data = right ADC; right data =right

ADC

11: left data = right ADC; right data = left

ADC

Table 8 ADC Data Output Configuration

PGA CONTROL

The PGA matches the input signal level to the ADC input range. The PGA gain is logarithmically

adjustable from +30dB to –17.25dB in 0.75dB steps. Each PGA can be controlled either by the user

or by the ALC function (see Automatic Level Control). When ALC is enabled for one or both

channels, then writing to the corresponding PGA control register has no effect.

The gain is independently adjustable on both Right and Left Line Inputs. Additionally, by controlling

the register bits LIVU and RIVU, the left and right gain settings can be simultaneously updated.

Setting the LZCEN and RZCEN bits enables a zero-cross detector which ensures that PGA gain

changes only occur when the signal is at zero, eliminating any zipper noise. If zero cross is enabled

a timeout is also available to update the gain if a zero cross does not occur. This function may be

enabled by setting TOEN in register R23 (17h).

The inputs can also be muted in the analogue domain under software control. The software control

registers are shown in Table 9. If zero crossing is enabled, it is necessary to enable zero cross

timeout to un-mute the input PGAs. This is because their outputs will not cross zero when muted.

Alternatively, zero cross can be disabled before sending the un-mute command.

WM8988 Datasheet(PDF) 18 Page - Wolfson Microelectronics plc

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