CY8C56LP datasheet(9/120 Pages) CYPRESS

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PRELIMINARY

PSoC® 5LP: CY8C56LP Family

Datasheet

Document Number: 001-84935 Rev. **

Page 9 of 120

3. Pin Descriptions

IDAC0, IDAC1, IDAC2, IDAC3

Low resistance output pin for high current DACs (IDAC).

Opamp0out, Opamp1out, Opamp2out, Opamp3out

High current output of uncommitted opamp[8].

Extref0, Extref1

External reference input to the analog system.

SAR0 EXTREF, SAR1 EXTREF

External references for SAR ADCs

Opamp0–, Opamp1–, Opamp2–, Opamp3–

Inverting input to uncommitted opamp.

Opamp0+, Opamp1+, Opamp2+, Opamp3+

Noninverting input to uncommitted opamp.

GPIO

General purpose I/O pin provides interfaces to the CPU, digital

peripherals, analog peripherals, interrupts, LCD segment drive,

and CapSense[8].

I2C0: SCL, I2C1: SCL

I2C SCL line providing wake from sleep on an address match. Any

I/O pin can be used for I2C SCL if wake from sleep is not required.

I2C0: SDA, I2C1: SDA

I2C SDA line providing wake from sleep on an address match. Any

I/O pin can be used for I2C SDA if wake from sleep is not required.

Ind

Inductor connection to boost pump.

kHz XTAL: Xo, kHz XTAL: Xi

32.768-kHz crystal oscillator pin.

MHz XTAL: Xo, MHz XTAL: Xi

4 to 25 MHz crystal oscillator pin.

nTRST

Optional JTAG Test Reset programming and debug port

connection to reset the JTAG connection.

SIO.

Special I/O provides interfaces to the CPU, digital

peripherals and interrupts with a programmable high threshold

voltage, analog comparator, high sink current, and high

impedance state when the device is unpowered.

SWDCK

Serial Wire Debug Clock programming and debug port connection.

SWDIO

Serial Wire Debug Input and Output programming and debug

port connection.

TCK

JTAG Test Clock programming and debug port connection.

TDI

JTAG Test Data In programming and debug port connection.

TDO

JTAG Test Data Out programming and debug port connection.

TMS

JTAG Test Mode Select programming and debug port connection.

TRACECLK

Cortex-M3 TRACEPORT connection, clocks TRACEDATA pins.

TRACEDATA[3:0].

Cortex-M3 TRACEPORT connections, output data.

SWV.

Single Wire Viewer output.

USBIO, D+

Provides D+ connection directly to a USB 2.0 bus. May be used

as a digital I/O pin; it is powered from VDDD instead of from a

VDDIO. Pins are Do Not Use (DNU) on devices without USB.

USBIO, D–

Provides D– connection directly to a USB 2.0 bus. May be used

as a digital I/O pin; it is powered from VDDD instead of from a

VDDIO. Pins are Do Not Use (DNU) on devices without USB.

VBOOST

Power sense connection to boost pump.

VBAT

Battery supply to boost pump.

VCCA

Output of the analog core regulator or the input to the

analog core.

Requires a 1uF capacitor to VSSA. The regulator

output is not designed to drive external circuits. Note that if you

use the device with an external core regulator (externally

regulated mode), the voltage applied to this pin must not

exceed the allowable range of 1.71 V to 1.89 V.

When using

the internal core regulator, (internally regulated mode, the

default), do not tie any power to this pin. For details see Power

System on page 24.

VCCD.

Output of the digital core regulator or the input to the digital

core.

The two VCCD pins must be shorted together, with the

trace between them as short as possible, and a 1uF capacitor to

VSSD. The regulator output is not designed to drive external

circuits. Note that if you use the device with an external core

regulator (externally regulated mode), the voltage applied to

this pin must not exceed the allowable range of 1.71 V to

1.89 V.

When using the internal core regulator (internally

regulated mode, the default), do not tie any power to this pin. For

details see Power System on page 24.

VDDA

Supply for all analog peripherals and analog core regulator.

VDDA must be the highest voltage present on the device. All

other supply pins must be less than or equal to VDDA.

VDDD

Supply for all digital peripherals and digital core regulator. VDDD

must be less than or equal to VDDA.

VSSA

Ground for all analog peripherals.

VSSB

Ground connection for boost pump.

VSSD

Ground for all digital logic and I/O pins.

Notes

8. GPIOs with opamp outputs are not recommended for use with CapSense.

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