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CY8C56LP Datasheet(PDF) 92 Page - Cypress Semiconductor |
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CY8C56LP Datasheet(HTML) 92 Page - Cypress Semiconductor |
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92 / 120 page  PRELIMINARY PSoC® 5LP: CY8C56LP Family Datasheet Document Number: 001-84935 Rev. ** Page 92 of 120 Figure 11-54. VDAC Full Scale Error vs Temperature, 1 V Mode Figure 11-55. VDAC Full Scale Error vs Temperature, 4 V Mode Figure 11-56. VDAC Operating Current vs Temperature, 1V Mode, Slow Mode Figure 11-57. VDAC Operating Current vs Temperature, 1 V Mode, Fast Mode Table 11-33. VDAC AC Specifications Parameter Description Conditions Min Typ Max Units FDAC Update rate 1 V scale – – 1000 ksps 4 V scale – – 250 ksps TsettleP Settling time to 0.1%, step 25% to 75% 1 V scale, Cload = 15 pF – 0.45 1 µs 4 V scale, Cload = 15 pF – 0.8 3.2 µs TsettleN Settling time to 0.1%, step 75% to 25% 1 V scale, Cload = 15 pF – 0.45 1 µs 4 V scale, Cload = 15 pF – 0.7 3 µs Voltage noise Range = 1 V, fast mode, VDDA = 5 V, 10 kHz –750 – nV/sqrtHz |
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